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ARM920T Core Module R/W Registers Issues ?
by Unknown on Dec 17, 2003
Not available!

Hi, dear elites

I monitor the bus behavior of core module CM920T by logic analyzer.
And I found that it needs about 20~30 cycles to read/write a external
AHB slave register. When I read or write 4 continuous address registers,
sequenctial transfer won't happen(HTRAN==2'b11) and still
need 20~30 cycles to operate. How can I reduce the read/write cycles
of CM920T? How can improve the performance of CM920T. The 920T
core's freq. is 50MHz and the AHB freq. is 15.36MHz(ext.) The test program
is just a simple R/W register and no other loading wrtiien in C.

The Integrator AP/CM system uses asynchronous bridges to allow connection
between differing Core Modules and these bridges(ASB->AHB).

I am wondering if there are anyony ever encountered the same problem for
driver response issues. We need to improve the r/w register cycles.

Appreciate for your any comments.



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