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Can I get the time integrating correlator's verilog source code?
by Unknown on Dec 24, 2003
Not available!
----- Original Message ----- From: mysticdude117 at y... To: cores at o... Date: Wed, 5 Nov 2003 15:40:41 +0100 Subject: Re: [oc] Can I get the time integrating correlator's verilog source code?
----- Original Message ----- From: sharma.amar at i... To: uzunlarovunc at h... , cores at o... Date: Fri, 12 Sep 2003 10:18:54 +0200 Subject: Re: [oc] Can I get the time integrating correlator's verilog source code?
> > > > > ----- Original Message ----- > From: uzunlarovunc at h... > To: myogananth at r... , cores at o... > Date: Sat, 12 Apr 2003 18:13:44 -0100 > Subject: [oc] Can I get the time integrating correlator's

verilog
> source code?
>
> > > > > ----- Original Message ----- > From: myogananth at r... > To: joe_zhao at s... , cores at o... > Date: Sun, 2 Feb 2003 10:42:18 -0100 > Subject: Re: [oc] Can I get the sdram controller by FPGA?

> (VHDL)
>
> >
> >
> > whether any project availble in low power

dissipiation
> viterbi
> > decoder > > design using verilog > > > > > > > > > > > > > > > > ----- Original Message ----- > > From: joe_zhao at s... > > To: cores at o... > > Date: Tue, 26 Nov 2002 10:02:48 -0100 > > Subject: Re: [oc] Can I get the sdram controller by

FPGA?
> (VHDL)
> >
> >
> >
> > I hope to get the sdram controller free core by

FPGA
> (VHDL).
> > > > Joe zhao > > > > 11/26 > > ----- Original Message ----- > > From: dheeraj_vij at r... > > To: cores at o... > > Date: Thu, 10 Oct 2002 11:43:51 -0100 > > Subject: Re: [oc] Can I get the > >
> > >
> > >
> > >
> > >
> > > ----- Original Message -----
> > > From: "=?gb2312?B?sNe35g==?="
baifeng at m...
>
> > > To: cores at o... > > > > Date: Tue, 5 Feb 2002 10:55:49 +0800 > > > Subject: Re: [oc] Can I get the "SDRAM

> controller
> VHDL"
> > or
> > Verilog
> > > Source Code?
> > >
> > >
> > >
> > > hai servan,
> > > Can u send me the the source

code
> of
> sdram
> > controller
> > > ?
> > > Thanks > > > baifeng > > > > > > ----- Original Message ----- > > > From: "I. Servan Uzun" isu at b...

>
> > > To: cores at o... > > > > Sent: Saturday, February 02, 2002

7:53 PM
> > > Subject: Re: [oc] Can I get the

"SDRAM
> controller
> > VHDL"
> > or
> > > Verilog
> > > Source Code?
> > >
> > >
> > > > Madhu,
> > > >
> > > > Below is the link for SDR SDRAM

> Controller
> > Reference
> > > Design
> > > >

> > >

> >
> http://www.altera.com/products/ip/altera/m-alt-sdr-sdram.shtml
> > > >
> > > > I didn' t searched for the

source
> code but
> it
> > must
> > be
> > > somewhere on
> > > > the website. If you can not find

it,
> I can
> send
> > VHDL
> > > source
> > > code to you
> > > > by e-mail.
> > > >
> > > > Regards,
> > > > - Servan
> > > >
> > > > ----- Original Message -----
> > > > From: "Madhusudhan Rao"
> > madhu_sudhana_rao at y...
> > >
> > > > To: cores at o... > > > > > Sent: Friday, February 01, 2002

11:23
> PM
> > > > Subject: Re: [oc] Can I get the

> "SDRAM
> > controller
> > VHDL"
> > > or
> > > Verilog Source
> > > > Code?
> > > >
> > > >
> > > > hai servan,
> > > > Can u give me the

address
> link
> for
> > the
> > source
> > > > code.
> > > >
> > > > Thanks
> > > > Madhu
> > > >
> > > > --- "I. Servan Uzun"
> isu at b...
> >
> > wrote:
> > > > > Altera has a SDRAM

> controller
> > megacore
> > function
> > > with
> > > > > an application note. I
> > > > > have
> > > > > used it with APEX20KE

> device at
> > 100MHz.
> > Source
> > > code
> > > > > of the core is also
> > > > > available in VHDL
> > > > > on its website.
> > > > >
> > > > > - Servan
> > > > >
> > > > > ----- Original Message

> -----
> > > > > From: "sphuynh"
> sphuynh at m...
> >
> > > > > To: cores at o...

>
> > > > > Sent: Thursday,

January 31,
> 2002
> 6:29
> > PM
> > > > > Subject: RE: [oc] Can

I get
> the
> > "SDRAM
> > > controller
> > > > > VHDL" or Verilog

Source
> > > > > Code?
> > > > >
> > > > >
> > > > > Xilinx have a

couple
> application
> > notes and
> > > source
> > > > > codes for SDRAM
> > > > > controller
> > > > > for their Virtex

and
> Spartan
> > family.
> > I'm
> > > not
> > > sure
> > > > > if this any useful to
> > > > > you. Below are

the
> links.
> > > > >
> > > > > DDR SDRAM

controller:
> > > > >
> > http://www.xilinx.com/xapp/xapp200.pdf
> > > > >
> > > > > SDR SDRAM

controller:
> > > > >
> > http://www.xilinx.com/xapp/xapp134.pdf
> > > > >
> > > > > Son Huynh
> > > > >
> > > > >
> > > > >
> > > > > -----Original

> Message-----
> > > > > From: hanz at c...
> > > > > [mailto:hanz at c... ]
> > > > > Sent: Tuesday,

January
> 29,
> 2002
> > 1:15
> > PM
> > > > > To: cores at o... > > > > > Subject: [oc] Can

I
> get the
> > "SDRAM
> > > controller
> > > > > VHDL" or Verilog

Source
> > > > > Code?
> > > > >
> > > > >
> > > > > I'm a master

source
> student
> in
> > KAIST.
> > > > >
> > > > > I've been

designed
> CMOS
> Digital
> > camera
> > > system,
> > > but
> > > > > I can't
> > > > >
> > > > > realize SDRAM

> controller
> using
> > Altera
> > Flex
> > > Chip.
> > > > >
> > > > > Can I get the

"SDRAM
> controller
> > VHDL"
> > or
> > > Verilog
> > > > > Source Code?
> > > > >
> > > > > Thank you.
> > > > >
> > > > >
> > > > >
> > > > > --
> > > > > To unsubscribe

from
> cores
> > mailing
> > list
> > > please
> > > > > visit
> > > > >

> > >
http://www.opencores.org/mailinglists.shtml
> > > > > --
> > > > > To unsubscribe

from
> cores
> > mailing
> > list
> > > please
> > > > > visit
> > > > >
> > http://www.opencores.org/mailinglists.shtml
> > > > >

> > > > >
> > > > >
> > > > >

> > > >
> > > >
> > > > =====
> > > > MadhusudhanaRao.M
> > > >
> > > >
> > > >

> > > >
> > > >
> > > >

> > >

> > >

> >

> >

>

>




Can I get the time integrating correlator's verilog source code?
by Unknown on Dec 24, 2003
Not available!
respected sir

i need the sdram controller source code in vhdl for my project
if u have please mail me


sachin shashikantrao pampattiwar

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