no use no use 1/1 no use no use
Willing to join an ongoing project
by TDJ on Jun 13, 2020
Posts: 4
Joined: May 23, 2020
Last seen: Jun 8, 2024
Hello All,

I have completed my Bachelor's in Electronics Engineering and have completed an industrial training in Advanced RTL Design and Verification.

I have good exposure to design and verification domain with the following qualifications:
* Good understanding of the ASIC and FPGA design flow
* Extensive experience in writing RTL models using Verilog HDL.
* Good experience in writing Testbenches using SystemVerilog and UVM
* Very good knowledge in verification methodologies
* Experience in using industry standard EDA tools for the front-end design and verification.

I am attaching here my Resume for further details about my skills and projects. I request you all to kindly give me an opportunity to contribute to your project. I would be very thankful and happy.

Tasmai Joshi
RE: Willing to join an ongoing project
by vikku on Jun 14, 2020
Posts: 1
Joined: May 18, 2020
Last seen: May 5, 2021
Hey can you help me to my project AMBA protocol

no use no use 1/1 no use no use
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