Background/Issue: From the previous work done on the FPGA, Spartan3, Uart 16550 core written in Verilog, is in use with HDLC controller as a means for the SDLC communication. Appears that the baud rate of the communication is set through sending the specific frequency to the UART 16550 core, in order to generate 921600 baud rate.
I have little experience in Verilog, and need to make the change of to SDLC communication to 1MHz, with keeping 921600 baud rate.

14.7456MHz entered to the Uart 16550 core input, via wb_clk_i port. is used what appears to generate (wb_clk_i input) the baud rate.
Could anyone guide me to generate the 921600 baud rate through parameter settings perhaps, or some other way, and to set the 1MHz SDLC communication rate.