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Problem in deciphering eth_Memory.v in testbench
by Unknown on Feb 17, 2004
Not available!
Dear All, 1. Wishbone standard says that during READ the Master will configure the SEL_O() indicating where it expects the data. In the eth_memory.v (as a part of the testbench with the EthernetIPCore) why we donot consider these SEL_O() input while reading too. We have considered only the least significant 2 bits of the ADDR_I(). However, that logic is also not very clear to me. (viz. in the comments it is written on those lines...that "word select", "half word select", "byte select" for various combinations.) Only first one (i.e. "word select" for "00" combination) is understood. 2. Wishbone specs asks for WISHBOME datasheet for WISHBONE compliant products. Where is one for our EthernetIP core? Could anybody help me clear the doubts? Thanking you in anticipation, Mayur __________________________________ Do you Yahoo!? Yahoo! Finance: Get your refund fast by filing online.
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