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7 wire Ethernet PHY (GPSI)
by Unknown on May 20, 2004
Not available!
I have a question concerning the Ethernet core. Unfortunately I have
an Ethernet PHY daughterboard I have to work with that only supports
the 10mbit, 7 wire, GPSI interface. (Limited PHY interface with data
being sent and received on single lines at 10mhz) My current plan is to
take the outgoing tx data nibble and serialize it for the PHY and in the
reverse direction, take the rx serial receive data and de-serialize it into
a nibble for the controller. Also, the clocks would be divided (10 MHz/4-
2.5 MHz) appropriately and the control signals would need to be re-

timed to sync with the incoming or out going nibbles. Not being all that
familiar with Ethernet, I just wanted to know if there are any obvious
reasons that this wouldnÂ’t work.

7 wire Ethernet PHY (GPSI)
by Unknown on May 21, 2004
Not available!
At least one thing you need to check and it is the bit order and see the order you send and the order your phy expect is in sync. remember that for example SFD which is 5d in byte or as many time conside in nibble system as d(1101) only as the 5 is treated like part of the preamble is send 1 than 0 than 1 than 1. it only tell you wether to shift right or left but you might want to spend few minuts to make sure than later see your packets "disapper" or come with error. have a nice day Illan -----Original Message----- From: bsibilsky@comcast.net [mailto:bsibilsky@comcast.net] Sent: Thursday, May 20, 2004 6:11 AM To: ethmac@opencores.org Subject: [ethmac] 7 wire Ethernet PHY (GPSI) I have a question concerning the Ethernet core. Unfortunately I have an Ethernet PHY daughterboard I have to work with that only supports the 10mbit, 7 wire, GPSI interface. (Limited PHY interface with data being sent and received on single lines at 10mhz) My current plan is to take the outgoing tx data nibble and serialize it for the PHY and in the reverse direction, take the rx serial receive data and de-serialize it into a nibble for the controller. Also, the clocks would be divided (10 MHz/4-
2.5 MHz) appropriately and the control signals would need to be re-
timed to sync with the incoming or out going nibbles. Not being all that familiar with Ethernet, I just wanted to know if there are any obvious reasons that this wouldn't work. _______________________________________________ http://www.opencores.org/mailman/listinfo/ethmac
no use no use 1/1 no use no use
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