no use no use 1/1 no use no use
Zynq7000 PS_PL Ethernet
by Max89 on Feb 8, 2021
Posts: 1
Joined: Jan 11, 2021
Last seen: Mar 3, 2021
Hello everybody! I have a problem like this, I have an ALINX ax7015 debug board with two network interfaces. I know that one of them is connected to the processor (PS) and the other to the FPGA (PL). Tell me how can I create Block Design using Xilinx Vivado 2019 to connect both network interfaces? FPGA zynq7015-clg485-2
no use no use 1/1 no use no use
© copyright 1999-2023, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.