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trouble wish I2C
by zzsz on Apr 21, 2018
Posts: 3
Joined: Mar 11, 2018
Last seen: Aug 27, 2018
I'm tryting to test the i2c_master_slave module,but it seem that it don't work. I'm have some problem in the module i2c_master_bit_ctrl,
// assign scl and sda output (always gnd)
assign scl_o = 1'b0;
assign sda_o = 1'b0;

how can the i2c work with scl and sda always connected to gnd?

I will be grateful if somebody can help me!
RE: trouble wish I2C
by robfinch on Apr 22, 2018
Posts: 27
Joined: Sep 29, 2005
Last seen: Sep 12, 2023
This confused me too, but if you look at the top level module there should be buffer enable signals like scl_padoe_n. I believe the I2C bus communicates by disabling the buffer and allowing the output to float high. When the buffer is enabled then the output is grounded. The scl_o isn't the final output signal to I2C.

RE: trouble wish I2C
by olof on Apr 22, 2018
Posts: 218
Joined: Feb 10, 2010
Last seen: Dec 17, 2018
If you want to understand it better, you can run the i2c testbench with FuseSoC. Just install FuseSoC and run "fusesoc sim i2c --vcd". The vcd file will end up in build/i2c/sim-$simulator/testlog.vcd (where $simulator is icarus, modelsim, xsim, rivierapro or isim depending on which simulator you are using)
no use no use 1/1 no use no use
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