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Newbie Wishbone question
by emakuh on Jun 17, 2009
emakuh
Posts: 2
Joined: Jun 12, 2009
Last seen: Oct 13, 2009
I am working with a TS-7300 ARM9 Linux board and was trying to use the OpenCore wishbone project built for the board. I don't have much experience working with verilog and right now I am just trying to modify the code to get some sort of output from one of the DIO pins. I posted the code I was using below to give some reference, but so far I have tried changing "dummyreg" with the following:


dummyreg dummyreg dummyreg[1]
None of those seem to have any effect on the DIO pins for the board, I think I am just not understanding the software, but if any of you have some insight I would greatly appreciate some feedback.


/*
* BEGIN USER-SERVICEABLE SECTION
*
* The default here is to alias the entire space onto one 32-bit register "dummyreg"
* On reset, it is set to 0xdeadbeef but then retains the value last written to it.
* The value of this register drives GPIO pins 9-40 on the FPGA connector described
* above.
*/

reg [31:0] dummyreg;

assign wb_ack_o = wb_cyc_i && wb_stb_i; /* 0-wait state WISHBONE */
assign wb_dat_o = dummyreg;
assign headerpin_oe_o[40:1] = 40'hffffffffff; /* All outputs */
assign headerpin_o[40:1] = {dummyreg, 8'd0};
assign irq_o = 1'b0;

always @(posedge wb_clk_i) begin
if (wb_rst_i) dummyreg else
---> My code was going in this else
end

/*
* END USER-SERVICEABLE SECTION
*/
RE: Newbie Wishbone question
by sebx86 on Jun 18, 2009
sebx86
Posts: 11
Joined: Sep 19, 2008
Last seen: May 16, 2020
I am working with a TS-7300 ARM9 Linux board and was trying to use the OpenCore wishbone project built for the board. I don't have much experience working with verilog and right now I am just trying to modify the code to get some sort of output from one of the DIO pins. I posted the code I was using below to give some reference, but so far I have tried changing "dummyreg" with the following:


dummyreg dummyreg dummyreg[1]
None of those seem to have any effect on the DIO pins for the board, I think I am just not understanding the software, but if any of you have some insight I would greatly appreciate some feedback.


/*
* BEGIN USER-SERVICEABLE SECTION
*
* The default here is to alias the entire space onto one 32-bit register "dummyreg"
* On reset, it is set to 0xdeadbeef but then retains the value last written to it.
* The value of this register drives GPIO pins 9-40 on the FPGA connector described
* above.
*/

reg [31:0] dummyreg;

assign wb_ack_o = wb_cyc_i && wb_stb_i; /* 0-wait state WISHBONE */
assign wb_dat_o = dummyreg;
assign headerpin_oe_o[40:1] = 40'hffffffffff; /* All outputs */
assign headerpin_o[40:1] = {dummyreg, 8'd0};
assign irq_o = 1'b0;

always @(posedge wb_clk_i) begin
if (wb_rst_i) dummyreg else
---> My code was going in this else
end

/*
* END USER-SERVICEABLE SECTION
*/


I used this code long long time ago, It worked for me.
Written like that, it should work.

Have you tried to simulate this piece of code ?

Have you tried to put a constant directly to the output ? Does this work ?

S├ębastien
RE: Newbie Wishbone question
by emakuh on Jun 18, 2009
emakuh
Posts: 2
Joined: Jun 12, 2009
Last seen: Oct 13, 2009
Well it turns out that it was actually working correctly, I just didn't understand how the board actually worked, but I've made some progress. Thanks though, I'll keep posting on here as I have questions.
no use no use 1/1 no use no use
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