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Need help to implement the parallel chien search algorithm for bch decoder
by zoomkrupesh on Nov 7, 2009
Posts: 5
Joined: Jun 1, 2008
Last seen: Dec 26, 2022

I want to implement parallel chien search algorithm on FPGA.I found some material in which there are two methods are shown to implement the parallel chien search algorithm.
In one method there are pt different g.f(2) multiplier(a^1,a^2,a^3,a^4....a^pt) are used.
while in other method there are only t multiplier are used where t = no.of error correction bits.This t multiplier used p times where p=no.of parallel data bits.

I want to implement the second one because it takes less time to implement only t multiplier.I am confused that how to initialize the register with lambda(output from the error polynomial block in bch decoder)

So can anyone guide me how to implement it.

One more thing, does any one know how to implement g.f constant multiplier in a easy way.I am designing g.f constant multiplier for g.f(2^13) and I am deriving the equation manually which takes lots of time.

Thanks in advance.


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