no use no use 1/1 no use no use
by av2kk on Jan 19, 2022
Posts: 1
Joined: Jan 14, 2022
Last seen: May 22, 2023
I am trying to integrate sdram_axi4 core into my Microblaze project with XPS 14.7 (ISE 14.7 web pack) custom board. What is the correct way to do it?
What I did so far is to create a top module as per the example given and tried to create a AXI4 Slave with the supplied sdram_axi.v , sdram_axi_core.v and sdram_axi_pmem.v files. When I try to create a new IP using this method, there are a number of signals not defined in the top module as shown in the attached screen shot. How do I go about ? Should I add these signals in the top module? Is this way ( creating a new IP using .v files) the correct method or is there a simpler way to integrate this IP to my project? I have experience in creating components in Quartus II but new to Xilinx. By the way I can not use Vivado as I my board is using Spartan6 which is not supported by Vivado.
Thank for any help.
sdram_axi4.JPG (127 kb)
no use no use 1/1 no use no use
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