Project maintainers


Name: ardufpga_ice40up5k
Created: May 2, 2020
Updated: May 4, 2020
SVN: Check description below for external links
Bugs: 0 reported / 0 solved
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Other project properties

Category:Prototype board
Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a
License: GPL

arduFPGA iCE40UP5K

The board is Open Source Hardware ( under GPLv2, non commercial usage, for commercial usage and custom designs please feel free to contact me ) and come with plenty of example designs around ATmega/Xmega and RISCv soft cores with the default PIO, UART, TWI, TIMER's, SPI and other peripherals that are found in an ATmega uC, all RTL source code is licensed under GPLv2.

arduFPGA iCE40UP5K V1.1 is a FPGA development board in arduino R3 format that is fully compatible with all arduino R3 extension boards that accept 3.3V signal levels and more because each IO pin can have every possible function, this board by default is governed by two boot-loaders to load the user applications from a uSD memory card, by default come with a GUI to navigate the uSD memory card and load and run arduboy compatible games or applications on a reduced ATmega32u4 soft-core design.

At this moment this board is in final stage of development, now I work on the softcore Mega/Xmega and RISCv designs and bootloaders firmware.

The user guide can be fond on

The repository for all designs and source code can be found on

The board will be available for purchase from

A demo video uploaded to youtube:

The url of the svn repository is: