fast behavioral transceiver simulation models

Project maintainers


Name: astron_sim_transceiver
Created: Aug 14, 2020
Updated: Aug 14, 2020
SVN Updated: Aug 20, 2020
SVN: Browse
Latest version: download (might take a bit to start...)
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Bugs: 0 reported / 0 solved
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Other project properties

Category:Testing / Verification
Development status:Mature
Additional info:
WishBone compliant: No
WishBone version: n/a
License: Others

Copyright 2020 ASTRON (Netherlands Institute for Radio Astronomy) P.O.Box 2, 7990 AA Dwingeloo, The Netherlands

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

About this core

This is fast behavioural simulation model of a gigabit trancseiver; a serializer and the corresponding deserializer.

These source files can work in any environment, however it is recommended to use the RadioHDL tool to easily generate project files for e.g. Modelsim, Quartus and Vivado (see 'About hdllib.cfg and the RadioHDL tool').

Test bench(es)

A self-checking test bench is included.


This core has the following dependencies:

Source files

The source files are listed hdllib.cfg.

More information about this core

Each source file comes with a header containing more information.

About hdllib.cfg and the RadioHDL tool

The hdllib.cfg file is included in all ASTRONs cores and is a config file that is detected by the RadioHDL development tool (also on OpenCores).

The source files are in order of dependency. However, some or all files could also be standalone.

The section 'test_bench_files' can list test benches, but also simulation-only source files that are not test benches.