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Name: bitserial
Created: Sep 17, 2020
Updated: Sep 17, 2020
SVN Updated: Sep 17, 2020
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star2you like it: star it!

Other project properties

Development status:Stable
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: BSD

This is a bit-serial CPU, a bit-serial CPU is one that processes N-bits (in this case 16) one at a time, most modern processors are bit-parallel, they computer all bits for an instruction in one clock cycle. This means that this processor is very slow, however it makes up for that by being very small, the entire project is only 73 slices (mostly taken up by a UART) on a Spartan-6 FPGA with the CPU itself taking 23 slices.

This processor is a niche one that may find use as an alternative to the picoblaze/KCPSM processors, one where floor space and routing between the CPU and block RAM may be of concern.

To prove that it is possible to do work with this processor a Forth implementation (which is most like the eForth variant) and cross compiler was written for this CPU, a C simulator is also available along with instructions in the projects on how to build and run it in the '' file. Once you have checked out the project, just type 'make run' on a system with both GNU make and C compiler installed, it comes with a pre-built eForth image (to rebuild it you will need gforth installed).

The VHDL project has been tested and works on a Nexys-3 development board and should be very easy to port to a new platforms.

The project is actually MIT licensed, but that is functionally equivalent to a 2-clause BSD license and 'MIT license' was not a drop down option.

Have fun!