DDR SDRAM Controller Core

Project maintainers


Name: ddr_sdr
Created: Dec 20, 2002
Updated: Jan 12, 2018
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 4 reported / 0 solved
Star6you like it: star it!

Other project properties

Category:Memory core
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a


The ddr_sdr controls read and write access of a programmable
logic device to a single 256 Mbit memory device. The 32-bit
wide user interface basically accepts two commands, read or
write. The control logic initializes the memory after reset
and issues refresh commands from time to time to ensure data
integrity. The data width to the memory device is 16 bits
wide and performs a double data rate operation at 100 MHz
clock rate.


- Version 1.0 available