This page contains files uploaded to the old opencores website as well as images and documents intended for use on other pages in this project. If you want to download this project or browse its svn, you can do so at the overview-page.
|2008-10-29 18:41||i2c_core_v02.vhd||this is the core istelf. it containd three processes, one for the master interface, the second for the slave and the third is for arbitration.
the master write mode is currently working in FPGA, XILINX x3s1500ft456.
master read will be tested soon, update will be posted.|
|as the name states||Show||Link||2012-06-05 08:03|