i8255 realisation in Verilog

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Name: i8255
Created: Nov 13, 2009
Updated: Dec 20, 2009
SVN Updated: Nov 22, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
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Bugs: 0 reported / 0 solved
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Other project properties

Category:Communication controller
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL


Complete implementation of i8255 PPI in fpga.

You may find some datasheets about here.

Verilog code has some modules:

PORTS - matches to the a,b,c. External world - inout tri-state bus. Internal circuit - datain and dataout buses.

port c divided by two parts - high and low.

GROUPS - represent group A and group B like in the real device. Group A controls port A and hight 4 bits of port C.

Group B controls port B and low 4 bits of port c.

Groups connected to ports with input/output data buses and control lines.

i8255 core - all external inputs and outputs like in real device. Operates groups. Connected to them with input/output buses.

Device doesn't use clock! It's main problem in realization. Issue pulls up with assignment delay to inout bus in iSim if we try to enable output to it from always block.ModelSim handles this stuff just fine.

P.S. Please, read news))


It's my first project on the FPGA scene. I want to improve myself in verilog and fpga.
And this project will be good testbench for my parallel project - easy to create simple gui controls( like LEDs, buttons, displays, etc)
in Python for famous simulators.