Name: minsoc
Created: Sep 18, 2009
Updated: Apr 20, 2013
SVN Updated: May 12, 2013
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 4 reported / 1 solved
Star8you like it: star it!

Other project properties

Category:System on Chip
Development status:Stable
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL


The Minimal OpenRISC System on Chip is a system on chip (SoC) implementation with standard IP cores available at OpenCores. This implementation consists of a standard project comprehending the standard IP cores necessary for a SoC embedding the OpenRISC implementation OR1200.

This project idea is to offer a synthesizable SoC which can be uploaded to every FPGA and be compatible with every FPGA board without the requirement of changing its code. In order to deliver such a project, the project has been based on a standard memory implementation and the Advanced Debug System, which allows system debug and software upload with the same cables used for FPGA configuration.

The adaptation of the project to a target board is made in 2 steps maximum. First, the “minsoc_defines.v” file has to be adjusted, generally one has to only uncomment his FPGA manufacturer and FPGA model definitions. After that, a constraint file for your specific pinout has to be created. Constraint files for standard boards can be found in the backend directory of the project.

Furthermore, the project offers working testbench and firmwares for its SoC. The current testbench can be run out of the box using Icarus Verilog v. 9.1. The firmwares are nearly the same of those of orpsocv2. The differences are for now, that the known UART "hello world" example now runs with interrupts and a new Ethernet example has been added to it.

To complete, an on-chip memory instance is provided to embed the CPU's firmware. The size of this memory can be adapted defining its address width inside of the same minsoc_defines.v file, affecting simulation and synthesis equally. This enables the customization of the SoC to the available resources of the target FPGA, for general purposes, or to the memory amount required by the target firmware, for custom implementation, e.g. ASIC.

An overview about the complete SoC and its external connections is on Figure 1.

System Features

-or1200 OpenRISC implementation

-Resizable onchip memory

-System frequency selection

-JTAG debug featuring a multitude of cables

-Start-up option to automatically load your firmware on start-up from an external SPI memory

-UART and Ethernet modules

-FPGA generic and specific code (Xilinx & Altera) for memory, clock adaptation (PLLs and DCMs) and JTAG Tap

-System configuration in a single definition file

-Example firmwares using UART and Ethernet

-Testbench included, for the simulation of exacly your configured system


All minsoc FPGA generic features have been simulated and proven to work.

The FPGA generic features have been tested on an FPGA implementation and are working. These comprehend the FPGA generic only modules, start-up, Ethernet, UART and or1200 OpenRISC; and the generic JTAG tap and the generic clock divider. Both, JTAG tap and clock divider, can optionally be FPGA specific. On the other hand, the generic memory cannot be implemented in an FPGA generic way, because the synthesizer does not allocate them to RAMs, consuming then all FPGA flip-flops.

The FPGA specific features, onchip memory, clock frequency adaptation and JTAG taps have to be tested for different FPGAs. Xilinx implementations differs in both instantiation and implementation for all modules. Altera differs perhaps in implementation, but the modules can be instantiated equally. A specific implementation of a clock frequency adaptation PLL for Altera has been recently added by Javier Almansa.

Test of FPGA specific features requires feedback from users, for now we have positive results from the following configurations:
-Xilinx, Spartan 3E (Spartan3E Starter Kit) (Thanks to Bakiri Mohammed)
-Xilinx, Spartan 3A (Spartan3A 1800 DSP Kit)
-Xilinx, Virtex 4 (ML405 board) (Thanks to Ravi Kumar)
-Xilinx, Virtex 5 (ML505 board) (Thanks to Evangelos Logaras)
-Altera, Cyclone II (Thanks to Nathan Yawn)
-Altera, Cyclone II (DE2-70 board) (Thanks to Alex Parrado)
-Altera, Cyclone III (Thanks to Davide Catani)
-Altera, Cyclone IV (Bemicro SDK board) (Thanks to Jean-Christophe Ricard)
-Altera, Stratix II (Thanks to Alex Parrado)

For now no configurations have been proven not to work.

How To

Information regarding the usage of MinSoC can be found in our wiki:

There, you will find guidance to retrieve and install the required tools, simulate and synthesize the design, and to run and debug the first firmware on your FPGA.

If you can improve the wiki, feel free do so. It is public. Update pages, create new ones and add links to them. This allow for quality as you find errors, correct the language or give hints to users doing the same thing as you.


If you have problems implementing the design or information regarding new tested platforms, want to contribute with a ucf file or are interested in implementing something for the project, contact our discussion group.

Send an email to:

This discussion group together with the wiki are the places for decision and planing of MinSoC's development. You can check latest maintainer's ideas and plans under: http://www.minsoc.compm:start