Neutal Net Perceptron for Pattern Recognition

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Name: neural_net_perceptron
Created: Jul 20, 2022
Updated: Jul 28, 2022
SVN Updated: Jul 28, 2022
SVN: Browse
Latest version: download (might take a bit to start...)
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Bugs: 0 reported / 0 solved
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Other project properties

Development status:Beta
Additional info:Design done, Specification done
WishBone compliant: Yes
WishBone version: B.4
License: GPL


VHDL IP Neural Net Perceptron core to train and test bipolar pattern pairs s:t. It doesn't use multiplier or DSP blocks and it uses generic on-chip memory. The memory is dynamically configurable by the user while running the core. A build-in auto-adjusting RD/WR wait state generator make this core very flexible to different FPGA vendors and families with on-chip memory areas. It also allows to load complete pre-defined data sets for further training or testing after shut down. Registers for Threshold, Offset, Bias and Epochs helps to setup the Neural Net for noisy or exact data environments. It comes with a specification document, all VHDL files, simulation scripts and a test bench which setup the core for a complete sample application. Last but not least there is a Wishbone, vB4 interface and an interrupt output to signalize the end of testing or training runs.

Please feel free to contact me for any reasons like ideas or error messages. I search for a translator to check the specification for English grammar and translate German to English.


  • Perceptron type Neural Net for pattern recognition
  • Bipolar s:t input data for training - Readout signed data for data sets and results after testing of pattern
  • Read from and write to any memory space (s, t, w matrix, bias and y)
  • Built-in training module with user configurable Max Epochs Counter
  • Threshold and Bias register for fine tuning of training
  • Signed data types on the Wishbone data bus without masking

  • Full synthesizable VHDL core for FPGA with on-chip memory

  • Wishbone compatible (V.B4)
  • User specific pre-configurable on-chip memory configuration
  • On-the-fly memory windowing within pre-configured memory space
  • No multiplications or DSP blocks - Only Add and Sub functions are used
  • Auto-adjusting memory Wait State generator for Reading and Writing
  • Enable/Disable Hardware Interrupt


  • All VHDL modules were verified by executing the sample application described in specification "Appendix B". All numerical results were compared against results of a test bench written in C.


  • Specification Revision 1.2 28-July-2022
  • Specification Revision 1.1 22-July-2022

    (Threshold value for Sample Project corrected from 0x25 to 0x20. Documented results of training and testing also corrected. Simulation scripts also corrected for new test bench version v05)

  • IP Core Revision 3.0 21-July-2022

  • Specification Revision 1.0 20-July-2022