Doin, Jonny

SPI Master/Slave Interface

i need more than one slave select wt modification should be done ?

Hi,
Thanks for the great tool. I'm a newbie at FPGA stuff, so I'm not sure how to approach this.

After many transfers (a few hours of running) moving data between a CPU and an FPGA using the SPI_SLAVE module, I find events where a few bits get missed. This means that SPI no longer works.  Is there some way to reset the spi slave? 

(I could reset the entire device, but I'm having a bugger of a time understanding the JTAG interface, so I'm not sure how to do it.)

Thanks for any advice.

How to reset after missed bits?

in the master_tx_fifo process i've added delay between di_req and wren_m. 
see below added code (last 5 line are mine) 
as result the wren occur when the master state machine value is 1. 
A new transaction does start. 
however, the sck_ena_reg is low during this transaction, and the SPI clock is disabled. 



master_tx_fifo_proc: process is 
variable fifo_memory : fifo_memory_type := 
(X"87654321",X"abcdef01",X"faceb007",X"10203049",X"85a5a5a5",X"7aaa5551",X"7adecabe",X"57564789", 
X"12345678",X"beefbeef",X"fee1600d",X"f158ba17",X"5ee1a7e3",X"101096da",X"600ddeed",X"deaddead"); 
variable fifo_head : integer range 0 to fifo_memory_size-1; 
begin 
-- synchronous rst_i 
wait until rst = '1'; 
wait until m_clk'event and m_clk = '1'; 
di_m '0'); 
wren_m fifo_head := 0; 
wait until rst = '0'; 
wait for 200 ns; 
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge 
-- wait until di_req_m = '1'; -- wait shift register request for data 
-- load next fifo contents into shift register 
for cnt in 0 to (fifo_memory_size/2)-1 loop 
fifo_head := cnt; -- pre-compute next pointer 
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge 
di_m wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge 
wren_m wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge 
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge 
wren_m wait until di_req_m = '1'; -- wait shift register request for data 
if cnt=1 then 
for i in 1 to 20 loop 
wait until m_clk'event and m_clk = '1'; 
end loop; 
end if;

false transaction

submitted by david.borokovsky@hp.com
in the master_tx_fifo process i've added delay between di_req and wren_m.
see below added code (last 5 line are mine)
as result the wren occur when the master state machine value is 1.
A new transaction does start.
however, the sck_ena_reg is low during this transaction, and the SPI clock is disabled.




master_tx_fifo_proc: process is
variable fifo_memory : fifo_memory_type :=
(X"87654321",X"abcdef01",X"faceb007",X"10203049",X"85a5a5a5",X"7aaa5551",X"7adecabe",X"57564789",
X"12345678",X"beefbeef",X"fee1600d",X"f158ba17",X"5ee1a7e3",X"101096da",X"600ddeed",X"deaddead");
variable fifo_head : integer range 0 to fifo_memory_size-1;
begin
-- synchronous rst_i
wait until rst = '1';
wait until m_clk'event and m_clk = '1';
di_m '0');
wren_m fifo_head := 0;
wait until rst = '0';
wait for 200 ns;
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
-- wait until di_req_m = '1'; -- wait shift register request for data
-- load next fifo contents into shift register
for cnt in 0 to (fifo_memory_size/2)-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
di_m wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m wait until di_req_m = '1'; -- wait shift register request for data
if cnt=1 then
for i in 1 to 20 loop
wait until m_clk'event and m_clk = '1';
end loop;
end if;

submitted by david.borokovsky@hp.com
in the master_tx_fifo process i've added delay between di_req and wren_m.
see below added code (last 5 line are mine)
as result the wren occur when the master state machine value is 1.
A new transaction does start. 
however, the sck_ena_reg is low during this transaction, and the SPI clock is disabled.




master_tx_fifo_proc: process is
variable fifo_memory : fifo_memory_type := 
	(X"87654321",X"abcdef01",X"faceb007",X"10203049",X"85a5a5a5",X"7aaa5551",X"7adecabe",X"57564789",
   X"12345678",X"beefbeef",X"fee1600d",X"f158ba17",X"5ee1a7e3",X"101096da",X"600ddeed",X"deaddead");
	variable fifo_head : integer range 0 to fifo_memory_size-1;
begin
        -- synchronous rst_i
	wait until rst = '1';
	wait until m_clk'event and m_clk = '1';
	di_m <= (others => '0');
	wren_m <= '0';
	fifo_head := 0;
   wait until rst = '0';
	wait for 200 ns;
	wait until m_clk'event and m_clk = '1';         -- sync fifo data load at next rising edge
--   wait until di_req_m = '1';                          -- wait shift register request for data
        -- load next fifo contents into shift register
   for cnt in 0 to (fifo_memory_size/2)-1 loop
   	fifo_head := cnt;                               -- pre-compute next pointer 
      wait until m_clk'event and m_clk = '1';         -- sync fifo data load at next rising edge
      di_m <= fifo_memory(fifo_head);                 -- place data into tx_data input bus
      wait until m_clk'event and m_clk = '1';         -- sync fifo data load at next rising edge
      wren_m <= '1';                                  -- write data into spi master
      wait until m_clk'event and m_clk = '1';         -- sync fifo data load at next rising edge
      wait until m_clk'event and m_clk = '1';         -- sync fifo data load at next rising edge
      wren_m <= '0';                                  -- remove write enable signal
      wait until di_req_m = '1';                      -- wait shift register request for data
		if cnt=1 then
			for i in 1 to 20 loop
		      wait until m_clk'event and m_clk = '1';
			end loop;			
		end if;

no clock on transfer sequence

no clock ontransfer sequence

The testbench is out of date. Some of the points:
- the ports of modules are outdated
- not fully parametrized, parameters are not propageted
- reset sequence works only out of luck, not because a working reset
- registers in the spi master and slave are not reseted properly
- no real loopback despide stated
- no check for bulk and single transfer
- no free running clocks of slave and master
- no stop condition for simulation
- ...
The Master and Slave itself looking interesting and far better than most alternatives. Unfortunatly it costed me some time to get the buggy testbench running.

Following you find my readapted testbench. It's not perfect, but functional. I tested it with modelsim (Questa Sim 10.0).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

library work;
use work.all;

ENTITY spi_loopback_test IS
    GENERIC (   
        N : positive := 8;                                 -- 32bit serial word length is default
        CPOL : std_logic := '0';                            -- SPI mode selection (mode 0 default)
        CPHA : std_logic := '1';                            -- CPOL = clock polarity, CPHA = clock phase.
        PREFETCH : positive := 3;                           -- prefetch lookahead cycles
        SPI_2X_CLK_DIV : positive := 1                      -- for a 100MHz sclk_i, yields a 10MHz SCK
    );                                          
END spi_loopback_test;
 
ARCHITECTURE behavior OF spi_loopback_test IS 

    --=========================================================
    -- Component declaration for the Unit Under Test (UUT)
    --=========================================================

	COMPONENT spi_loopback
	PORT(
		m_clk_i : IN std_logic;
		m_rst_i : IN std_logic;
		m_spi_miso_i : IN std_logic;
		m_di_i : IN std_logic_vector(N-1 downto 0);
		m_wren_i : IN std_logic;
		s_clk_i : IN std_logic;
		s_spi_ssel_i : IN std_logic;
		s_spi_sck_i : IN std_logic;
		s_spi_mosi_i : IN std_logic;
		s_di_i : IN std_logic_vector(N-1 downto 0);
		s_wren_i : IN std_logic;          
		m_spi_ssel_o : OUT std_logic;
		m_spi_sck_o : OUT std_logic;
		m_spi_mosi_o : OUT std_logic;
		m_di_req_o : OUT std_logic;
		m_do_valid_o : OUT std_logic;
		m_do_o : OUT std_logic_vector(N-1 downto 0);
		m_do_transfer_o : OUT std_logic;
		m_wren_o : OUT std_logic;
		-- m_wren_ack_o : OUT std_logic;
		m_rx_bit_reg_o : OUT std_logic;
		m_state_dbg_o : OUT std_logic_vector(5 downto 0);
		m_core_clk_o : OUT std_logic;
		m_core_n_clk_o : OUT std_logic;
		m_sh_reg_dbg_o : OUT std_logic_vector(N-1 downto 0);
		s_spi_miso_o : OUT std_logic;
		s_di_req_o : OUT std_logic;
		s_do_valid_o : OUT std_logic;
		s_do_o : OUT std_logic_vector(N-1 downto 0);
		s_do_transfer_o : OUT std_logic;
		s_wren_o : OUT std_logic;
		-- s_wren_ack_o : OUT std_logic;
		-- s_rx_bit_reg_o : OUT std_logic;
		s_state_dbg_o : OUT std_logic_vector(5 downto 0)
		);
	END COMPONENT;

    --=========================================================
    -- constants
    --=========================================================
    constant fifo_memory_size : integer := 16;
    shared variable ENDSIM : boolean;
    
    --=========================================================
    -- types
    --=========================================================
    type fifo_memory_type is array (0 to fifo_memory_size-1) of std_logic_vector (31 downto 0);

    --=========================================================
    -- signals to connect the instances
    --=========================================================
    -- internal clk and rst
    signal m_clk : std_logic := '0';                -- clock domain for the master parallel interface. Must be faster than spi bus sck.
    signal s_clk : std_logic := '0';                -- clock domain for the slave parallel interface. Must be faster than spi bus sck.
    signal rst : std_logic := 'U';
    -- spi bus wires
    signal spi_sck : std_logic;
    signal spi_ssel : std_logic;
    signal spi_miso : std_logic;
    signal spi_mosi : std_logic;
    -- master parallel interface
    signal di_m : std_logic_vector (N-1 downto 0) := (others => '0');
    signal do_m : std_logic_vector (N-1 downto 0) := (others => 'U');
    signal do_valid_m : std_logic;
    signal do_transfer_m : std_logic;
    signal di_req_m : std_logic;
    signal wren_m : std_logic := '0';
    signal wren_o_m : std_logic := 'U';
    -- signal wren_ack_o_m : std_logic := 'U';
    signal rx_bit_reg_m : std_logic;
    signal state_m : std_logic_vector (5 downto 0);
    signal core_clk_o_m : std_logic;
    signal core_n_clk_o_m : std_logic;
    signal sh_reg_m : std_logic_vector (N-1 downto 0) := (others => '0');
    -- slave parallel interface
    signal di_s : std_logic_vector (N-1 downto 0) := (others => '0');
    signal do_s : std_logic_vector (N-1 downto 0);
    signal do_valid_s : std_logic;
    signal do_transfer_s : std_logic;
    signal di_req_s : std_logic;
    signal wren_s : std_logic := '0';
    signal wren_o_s : std_logic := 'U';
    -- signal wren_ack_o_s : std_logic := 'U';
    -- signal rx_bit_reg_s : std_logic;
    signal state_s : std_logic_vector (5 downto 0);
    -- signal sh_reg_s : std_logic_vector (N-1 downto 0);

    --=========================================================
    -- Clock period definitions
    --=========================================================
    constant m_clk_period : time := 11 ns;          -- 100MHz master parallel clock
    constant s_clk_period : time :=  9 ns;          -- 100MHz slave parallel clock
    
BEGIN
 
    --=========================================================
    -- Component instantiation for the Unit Under Test (UUT)
    --=========================================================

    Inst_spi_loopback: entity work.spi_loopback(Structural)
         generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
   -- Inst_spi_loopback: spi_loopback
    port map(
        ----------------MASTER-----------------------
        m_clk_i => m_clk,
        m_rst_i => rst,
        m_spi_ssel_o => spi_ssel,
        m_spi_sck_o => spi_sck,
        m_spi_mosi_o => spi_mosi,
        m_spi_miso_i => spi_miso,
        m_di_req_o => di_req_m,
        m_di_i => di_m,
        m_wren_i => wren_m,
        m_do_valid_o => do_valid_m,
        m_do_o => do_m,
        ----- debug -----
        m_do_transfer_o => do_transfer_m,
        m_wren_o => wren_o_m,
        -- m_wren_ack_o => wren_ack_o_m,
        m_rx_bit_reg_o => rx_bit_reg_m,
        -- m_state_dbg_o => state_m,
        m_core_clk_o => core_clk_o_m,
        m_core_n_clk_o => core_n_clk_o_m,
        m_sh_reg_dbg_o => sh_reg_m,
        ----------------SLAVE-----------------------
        s_clk_i => s_clk,
        s_spi_ssel_i => spi_ssel,
        s_spi_sck_i => spi_sck,
        s_spi_mosi_i => spi_mosi,
        s_spi_miso_o => spi_miso,
        s_di_req_o => di_req_s,
        s_di_i => di_s,
        s_wren_i => wren_s,
        s_do_valid_o => do_valid_s,
        s_do_o => do_s,
        ----- debug -----
        s_do_transfer_o => do_transfer_s,
        s_wren_o => wren_o_s
        -- s_wren_ack_o => wren_ack_o_s
        -- s_rx_bit_reg_o => rx_bit_reg_s
        -- s_state_dbg_o => state_s
        -- s_sh_reg_dbg_o => sh_reg_s
    );

    --=========================================================
    -- Clock generator processes
    --=========================================================
    m_clk_process : process
    begin
        if ENDSIM=false then
            m_clk <= '0';
            wait for m_clk_period/2;
            m_clk <= '1';
            wait for m_clk_period/2;
        else
            wait;
        end if;
    end process m_clk_process;

    s_clk_process : process
    begin
        if ENDSIM=false then
            s_clk <= '0';
            wait for s_clk_period/2;
            s_clk <= '1';
            wait for s_clk_period/2;
        else
            wait;
        end if;
    end process s_clk_process;

    --=========================================================
    -- rst_i process
    --=========================================================
    rst <= '0', '1' after 20 ns, '0' after 100 ns; -- Error: High or Low active Reset?!
    
    
    --=========================================================
    -- Master interface process
    --=========================================================
    master_tx_fifo_proc: process is
        variable fifo_memory : fifo_memory_type := 
            (X"87654321",X"abcdef01",X"faceb007",X"10203049",X"85a5a5a5",X"7aaa5551",X"7adecabe",X"57564789",
             X"12345678",X"beefbeef",X"fee1600d",X"f158ba17",X"5ee1a7e3",X"101096da",X"600ddeed",X"deaddead");
        variable fifo_head : integer range 0 to fifo_memory_size-1;
        variable mapping : std_logic_vector (31 downto 0);
    begin
        wait until m_clk'event and m_clk = '1';
        di_m <= (others => '0');
        wren_m <= '0';
        fifo_head := 0;
        wait until rst = '1';
        wait until rst = '0';
        wait until m_clk'event and m_clk = '1';             -- 
        wait until m_clk'event and m_clk = '1';             -- 
        -- Error: Master output di_req_o is not sensitive for reset: wait until di_req_m = '1'; -- wait shift register request for data
        for cnt in 0 to (fifo_memory_size/2)-1 loop
            fifo_head := cnt;                               -- pre-compute next pointer 
            wait until m_clk'event and m_clk = '1';         -- 
            mapping := fifo_memory(fifo_head);              -- place data into tx_data input bus
            di_m <= mapping(N-1 downto 0);                  -- place data into tx_data input bus
            wait until m_clk'event and m_clk = '1';         -- 
            wren_m <= '1';                                  -- write data into spi master
            wait until m_clk'event and m_clk = '1';         -- 
            wait until m_clk'event and m_clk = '1';         -- 
            wren_m <= '0';                                  -- remove write enable signal
            wait until di_req_m = '1';                      -- wait shift register request for data
            wait until m_clk'event and m_clk = '1';         -- 
            wait until m_clk'event and m_clk = '1';         -- bigger break to see single byte transmission
            wait until m_clk'event and m_clk = '1';         -- 
            wait until m_clk'event and m_clk = '1';         -- 
            wait until m_clk'event and m_clk = '1';         -- 
            wait until m_clk'event and m_clk = '1';         -- 
            wait until m_clk'event and m_clk = '1';         -- 
            wait until m_clk'event and m_clk = '1';         -- 
        end loop;
        
        -- same error again: wait until spi_ssel = '1';
        wait for 1000 ns;
        for cnt in (fifo_memory_size/2) to fifo_memory_size-1 loop
            fifo_head := cnt;                               -- pre-compute next pointer 
            wait until m_clk'event and m_clk = '1';         -- 
            mapping := fifo_memory(fifo_head);              -- place data into tx_data input bus
            di_m <= mapping(N-1 downto 0);                  -- place data into tx_data input bus
            wait until m_clk'event and m_clk = '1';         -- 
            wren_m <= '1';                                  -- write data into spi master
            wait until m_clk'event and m_clk = '1';         -- 
            wait until m_clk'event and m_clk = '1';         -- 
            wren_m <= '0';                                  -- remove write enable signal
            wait until di_req_m = '1';                      -- wait shift register request for data
        end loop;
        
        wait for 1000 ns;
        ENDSIM := true;
        wait;
    end process master_tx_fifo_proc;


    --=========================================================
    -- Slave interface process
    --=========================================================
    di_s <= do_s;                                           -- loop data from output to input
    
    slave_tx_fifo_proc: process is
    begin
        wren_s <= '0';
        while 1 = 1 loop
            wait until di_req_s = '1';                      -- wait shift register request for data
            wait until s_clk'event and s_clk = '1';         -- 
            wait until s_clk'event and s_clk = '1';         -- 
            wren_s <= '1';                                  -- write data into shift register
            wait until s_clk'event and s_clk = '1';         -- 
            wait until s_clk'event and s_clk = '1';         -- 
            wren_s <= '0';                                  -- remove write enable signal
        end loop;
        wait;
    end process slave_tx_fifo_proc;
 
END ARCHITECTURE behavior;

Testbench Out of Date

Hello
I am using Altera Quartus 12.1 and SPI_MASTER version: v1.15.0136

When I put the signal rst_i = '1 'or the system is in stand, with no data to transmit clock SCLK keeps coming. Is not maintained at a constant level '1 '. It may be problem synthesizer or always wrong?

settings are:
N => 8
CPOL => '1 ',
CPHA => '1 ',
PREFETCH => 1,
SPI_2X_CLK_DIV => 2

sclk_i = pclk_i = 50 Mhz
spi clock = 25 Mhz

I can send a trap to the values ??of inputs and outputs. 
Tested on a FPGA (Cyclone IV)

Problem with reset SPI MASTER

The state machine encoding is currently a binary counter, representing bit 'N'.
This results in the smallest area, but is the least secure encoding. Depending on the P&R, path delays can create metastates during the state transitions, that can give rise to glitches under certain circunstances.

The state mapping should avoid this by using a minimized transition encoding, like gray or johnson.

state encoding

The documentation is very outdated and incomplete. It will be revised and updated.

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SPI Master/Slave Interface