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Written in:
Any language
VHDL
Verilog & VHDL
Verilog
SystemC
Bluespec
C/C++
Other
Stage:
Any stage
Planning
Mature
Alpha
Beta
Stable
License:
Any license
GPL
LGPL
BSD
CERN-OHL-S
CERN-OHL-L
CERN-OHL2-P
Others
Wishbone version:
Any version
B.3
B.4
ASIC proven
Design done
FPGA proven
Specification done
OpenCores Certified
Arithmetic core
18
Prototype board
8
Communication controller
47
Coprocessor
3
Crypto core
13
DSP core
8
ECC core
6
Library
5
Memory core
10
Other
28
Processor
46
System on Chip
16
System on Module
1
System controller
1
Testing / Verification
9
Video controller
13
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