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Written in:
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VHDL
Verilog & VHDL
Verilog
SystemC
Bluespec
C/C++
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Stage:
Any stage
Planning
Mature
Alpha
Beta
Stable
License:
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GPL
LGPL
BSD
CERN-OHL-S
CERN-OHL-L
CERN-OHL2-P
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Wishbone version:
Any version
B.3
B.4
ASIC proven
Design done
FPGA proven
Specification done
OpenCores Certified
Arithmetic core
9
Prototype board
3
Communication controller
20
Coprocessor
2
Crypto core
5
DSP core
3
Memory core
3
Other
7
Processor
12
System on Chip
10
Testing / Verification
1
Video controller
1
Uncategorized
1
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