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// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.
 
// PROGRAM              "Quartus II 64-Bit"
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED              "Sat Dec 10 09:01:30 2016"
 
module alu_flags(
        ctl_flags_oe,
        ctl_flags_bus,
        ctl_flags_alu,
        alu_sf_out,
        alu_yf_out,
        alu_xf_out,
        ctl_flags_nf_set,
        alu_zero,
        shift_cf_out,
        alu_core_cf_out,
        daa_cf_out,
        ctl_flags_cf_set,
        ctl_flags_cf_cpl,
        pf_sel,
        ctl_flags_cf_we,
        ctl_flags_sz_we,
        ctl_flags_xy_we,
        ctl_flags_hf_we,
        ctl_flags_pf_we,
        ctl_flags_nf_we,
        ctl_flags_cf2_we,
        ctl_flags_hf_cpl,
        ctl_flags_use_cf2,
        ctl_flags_hf2_we,
        ctl_flags_nf_clr,
        ctl_alu_zero_16bit,
        clk,
        ctl_flags_cf2_sel_shift,
        ctl_flags_cf2_sel_daa,
        nhold_clk_wait,
        flags_sf,
        flags_zf,
        flags_hf,
        flags_pf,
        flags_cf,
        flags_nf,
        flags_cf_latch,
        flags_hf2,
        db
);
 
 
input wire      ctl_flags_oe;
input wire      ctl_flags_bus;
input wire      ctl_flags_alu;
input wire      alu_sf_out;
input wire      alu_yf_out;
input wire      alu_xf_out;
input wire      ctl_flags_nf_set;
input wire      alu_zero;
input wire      shift_cf_out;
input wire      alu_core_cf_out;
input wire      daa_cf_out;
input wire      ctl_flags_cf_set;
input wire      ctl_flags_cf_cpl;
input wire      pf_sel;
input wire      ctl_flags_cf_we;
input wire      ctl_flags_sz_we;
input wire      ctl_flags_xy_we;
input wire      ctl_flags_hf_we;
input wire      ctl_flags_pf_we;
input wire      ctl_flags_nf_we;
input wire      ctl_flags_cf2_we;
input wire      ctl_flags_hf_cpl;
input wire      ctl_flags_use_cf2;
input wire      ctl_flags_hf2_we;
input wire      ctl_flags_nf_clr;
input wire      ctl_alu_zero_16bit;
input wire      clk;
input wire      ctl_flags_cf2_sel_shift;
input wire      ctl_flags_cf2_sel_daa;
input wire      nhold_clk_wait;
output wire     flags_sf;
output wire     flags_zf;
output wire     flags_hf;
output wire     flags_pf;
output wire     flags_cf;
output wire     flags_nf;
output wire     flags_cf_latch;
output reg      flags_hf2;
inout wire      [7:0] db;
 
reg     flags_xf;
reg     flags_yf;
wire    [1:0] sel;
reg     DFFE_inst_latch_hf;
wire    SYNTHESIZED_WIRE_0;
wire    SYNTHESIZED_WIRE_1;
wire    SYNTHESIZED_WIRE_2;
wire    SYNTHESIZED_WIRE_3;
wire    SYNTHESIZED_WIRE_4;
wire    SYNTHESIZED_WIRE_5;
wire    SYNTHESIZED_WIRE_6;
wire    SYNTHESIZED_WIRE_7;
reg     SYNTHESIZED_WIRE_39;
wire    SYNTHESIZED_WIRE_8;
wire    SYNTHESIZED_WIRE_9;
wire    SYNTHESIZED_WIRE_10;
wire    SYNTHESIZED_WIRE_11;
wire    SYNTHESIZED_WIRE_12;
wire    SYNTHESIZED_WIRE_13;
wire    SYNTHESIZED_WIRE_14;
wire    SYNTHESIZED_WIRE_15;
wire    SYNTHESIZED_WIRE_16;
wire    SYNTHESIZED_WIRE_17;
wire    SYNTHESIZED_WIRE_18;
wire    SYNTHESIZED_WIRE_19;
wire    SYNTHESIZED_WIRE_20;
wire    SYNTHESIZED_WIRE_21;
wire    SYNTHESIZED_WIRE_22;
reg     DFFE_inst_latch_sf;
wire    SYNTHESIZED_WIRE_23;
reg     DFFE_inst_latch_pf;
reg     DFFE_inst_latch_nf;
wire    SYNTHESIZED_WIRE_24;
wire    SYNTHESIZED_WIRE_25;
wire    SYNTHESIZED_WIRE_26;
wire    SYNTHESIZED_WIRE_27;
wire    SYNTHESIZED_WIRE_28;
wire    SYNTHESIZED_WIRE_29;
wire    SYNTHESIZED_WIRE_40;
wire    SYNTHESIZED_WIRE_32;
wire    SYNTHESIZED_WIRE_33;
wire    SYNTHESIZED_WIRE_34;
wire    SYNTHESIZED_WIRE_35;
wire    SYNTHESIZED_WIRE_36;
wire    SYNTHESIZED_WIRE_37;
reg     DFFE_inst_latch_cf;
reg     DFFE_inst_latch_cf2;
wire    SYNTHESIZED_WIRE_38;
 
assign  flags_sf = DFFE_inst_latch_sf;
assign  flags_zf = SYNTHESIZED_WIRE_39;
assign  flags_hf = SYNTHESIZED_WIRE_23;
assign  flags_pf = DFFE_inst_latch_pf;
assign  flags_cf = SYNTHESIZED_WIRE_24;
assign  flags_nf = DFFE_inst_latch_nf;
assign  flags_cf_latch = DFFE_inst_latch_cf;
assign  SYNTHESIZED_WIRE_38 = 0;
 
 
 
assign  SYNTHESIZED_WIRE_10 = db[7] & ctl_flags_bus;
 
assign  SYNTHESIZED_WIRE_17 = alu_xf_out & ctl_flags_alu;
 
assign  SYNTHESIZED_WIRE_20 = db[2] & ctl_flags_bus;
 
assign  SYNTHESIZED_WIRE_19 = pf_sel & ctl_flags_alu;
 
assign  SYNTHESIZED_WIRE_2 = db[1] & ctl_flags_bus;
 
assign  SYNTHESIZED_WIRE_23 = DFFE_inst_latch_hf ^ ctl_flags_hf_cpl;
 
assign  SYNTHESIZED_WIRE_22 = db[0] & ctl_flags_bus;
 
assign  SYNTHESIZED_WIRE_21 = ctl_flags_alu & alu_core_cf_out;
 
assign  SYNTHESIZED_WIRE_8 =  ~ctl_flags_cf2_we;
 
assign  SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_0 ^ ctl_flags_cf_cpl;
 
assign  SYNTHESIZED_WIRE_1 = alu_sf_out & ctl_flags_alu;
 
assign  SYNTHESIZED_WIRE_9 = alu_sf_out & ctl_flags_alu;
 
assign  SYNTHESIZED_WIRE_5 = ctl_flags_nf_set | SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
 
assign  SYNTHESIZED_WIRE_37 = SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_4;
 
 
assign  SYNTHESIZED_WIRE_32 = SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_6;
 
assign  SYNTHESIZED_WIRE_6 =  ~ctl_flags_nf_clr;
 
assign  SYNTHESIZED_WIRE_7 =  ~ctl_alu_zero_16bit;
 
assign  SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_39;
 
assign  SYNTHESIZED_WIRE_27 = ctl_flags_cf_we & nhold_clk_wait & SYNTHESIZED_WIRE_8;
 
assign  SYNTHESIZED_WIRE_29 = ctl_flags_cf2_we & nhold_clk_wait;
 
assign  SYNTHESIZED_WIRE_12 = db[6] & ctl_flags_bus;
 
assign  SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_9 | SYNTHESIZED_WIRE_10;
 
assign  SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12;
 
assign  SYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14;
 
assign  SYNTHESIZED_WIRE_40 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
 
assign  SYNTHESIZED_WIRE_35 = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18;
 
assign  SYNTHESIZED_WIRE_33 = SYNTHESIZED_WIRE_19 | SYNTHESIZED_WIRE_20;
 
assign  SYNTHESIZED_WIRE_11 = alu_zero & ctl_flags_alu;
 
assign  SYNTHESIZED_WIRE_26 = SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22;
 
assign  db[7] = ctl_flags_oe ? DFFE_inst_latch_sf : 1'bz;
 
assign  SYNTHESIZED_WIRE_14 = db[5] & ctl_flags_bus;
 
assign  db[6] = ctl_flags_oe ? SYNTHESIZED_WIRE_39 : 1'bz;
 
assign  db[5] = ctl_flags_oe ? flags_yf : 1'bz;
 
assign  db[4] = ctl_flags_oe ? SYNTHESIZED_WIRE_23 : 1'bz;
 
assign  db[3] = ctl_flags_oe ? flags_xf : 1'bz;
 
assign  db[2] = ctl_flags_oe ? DFFE_inst_latch_pf : 1'bz;
 
assign  db[1] = ctl_flags_oe ? DFFE_inst_latch_nf : 1'bz;
 
assign  db[0] = ctl_flags_oe ? SYNTHESIZED_WIRE_24 : 1'bz;
 
assign  SYNTHESIZED_WIRE_13 = alu_yf_out & ctl_flags_alu;
 
assign  SYNTHESIZED_WIRE_0 = ctl_flags_cf_set | SYNTHESIZED_WIRE_25;
 
assign  SYNTHESIZED_WIRE_16 = db[4] & ctl_flags_bus;
 
assign  SYNTHESIZED_WIRE_15 = alu_core_cf_out & ctl_flags_alu;
 
assign  SYNTHESIZED_WIRE_18 = db[3] & ctl_flags_bus;
 
 
always@(posedge clk)
begin
if (SYNTHESIZED_WIRE_27)
        begin
        DFFE_inst_latch_cf <= SYNTHESIZED_WIRE_26;
        end
end
 
 
always@(posedge clk)
begin
if (SYNTHESIZED_WIRE_29)
        begin
        DFFE_inst_latch_cf2 <= SYNTHESIZED_WIRE_28;
        end
end
 
 
always@(posedge clk)
begin
if (ctl_flags_hf_we)
        begin
        DFFE_inst_latch_hf <= SYNTHESIZED_WIRE_40;
        end
end
 
 
always@(posedge clk)
begin
if (ctl_flags_hf2_we)
        begin
        flags_hf2 <= SYNTHESIZED_WIRE_40;
        end
end
 
 
always@(posedge clk)
begin
if (ctl_flags_nf_we)
        begin
        DFFE_inst_latch_nf <= SYNTHESIZED_WIRE_32;
        end
end
 
 
always@(posedge clk)
begin
if (ctl_flags_pf_we)
        begin
        DFFE_inst_latch_pf <= SYNTHESIZED_WIRE_33;
        end
end
 
 
always@(posedge clk)
begin
if (ctl_flags_sz_we)
        begin
        DFFE_inst_latch_sf <= SYNTHESIZED_WIRE_34;
        end
end
 
 
always@(posedge clk)
begin
if (ctl_flags_xy_we)
        begin
        flags_xf <= SYNTHESIZED_WIRE_35;
        end
end
 
 
always@(posedge clk)
begin
if (ctl_flags_xy_we)
        begin
        flags_yf <= SYNTHESIZED_WIRE_36;
        end
end
 
 
always@(posedge clk)
begin
if (ctl_flags_sz_we)
        begin
        SYNTHESIZED_WIRE_39 <= SYNTHESIZED_WIRE_37;
        end
end
 
 
alu_mux_2       b2v_inst_mux_cf(
        .in0(DFFE_inst_latch_cf),
        .in1(DFFE_inst_latch_cf2),
        .sel1(ctl_flags_use_cf2),
        .out(SYNTHESIZED_WIRE_25));
 
 
alu_mux_4       b2v_inst_mux_cf2(
        .in0(alu_core_cf_out),
        .in1(shift_cf_out),
        .in2(daa_cf_out),
        .in3(SYNTHESIZED_WIRE_38),
        .sel(sel),
        .out(SYNTHESIZED_WIRE_28));
 
assign  sel[0] = ctl_flags_cf2_sel_shift;
assign  sel[1] = ctl_flags_cf2_sel_daa;
 
endmodule

Line No.	Rev	Author	Line
1	3	gdevic	`// Copyright (C) 1991-2013 Altera Corporation`
2			`// Your use of Altera Corporation's design tools, logic functions`
3			`// and other software and tools, and its AMPP partner logic`
4			`// functions, and any output files from any of the foregoing`
5			`// (including device programming or simulation files), and any`
6			`// associated documentation or information are expressly subject`
7			`// to the terms and conditions of the Altera Program License`
8			`// Subscription Agreement, Altera MegaCore Function License`
9			`// Agreement, or other applicable license agreement, including,`
10			`// without limitation, that your use is for the sole purpose of`
11			`// programming logic devices manufactured by Altera and sold by`
12			`// Altera or its authorized distributors. Please refer to the`
13			`// applicable agreement for further details.`
14
15			`// PROGRAM "Quartus II 64-Bit"`
16			`// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"`
17	16	gdevic	`// CREATED "Sat Dec 10 09:01:30 2016"`
18	3	gdevic
19			`module alu_flags(`
20			`ctl_flags_oe,`
21			`ctl_flags_bus,`
22			`ctl_flags_alu,`
23			`alu_sf_out,`
24			`alu_yf_out,`
25			`alu_xf_out,`
26			`ctl_flags_nf_set,`
27			`alu_zero,`
28			`shift_cf_out,`
29			`alu_core_cf_out,`
30			`daa_cf_out,`
31			`ctl_flags_cf_set,`
32			`ctl_flags_cf_cpl,`
33			`pf_sel,`
34			`ctl_flags_cf_we,`
35			`ctl_flags_sz_we,`
36			`ctl_flags_xy_we,`
37			`ctl_flags_hf_we,`
38			`ctl_flags_pf_we,`
39			`ctl_flags_nf_we,`
40			`ctl_flags_cf2_we,`
41			`ctl_flags_hf_cpl,`
42			`ctl_flags_use_cf2,`
43			`ctl_flags_hf2_we,`
44			`ctl_flags_nf_clr,`
45			`ctl_alu_zero_16bit,`
46			`clk,`
47	8	gdevic	`ctl_flags_cf2_sel_shift,`
48			`ctl_flags_cf2_sel_daa,`
49	16	gdevic	`nhold_clk_wait,`
50	3	gdevic	`flags_sf,`
51			`flags_zf,`
52			`flags_hf,`
53			`flags_pf,`
54			`flags_cf,`
55			`flags_nf,`
56			`flags_cf_latch,`
57			`flags_hf2,`
58			`db`
59			`);`
60
61
62			`input wire ctl_flags_oe;`
63			`input wire ctl_flags_bus;`
64			`input wire ctl_flags_alu;`
65			`input wire alu_sf_out;`
66			`input wire alu_yf_out;`
67			`input wire alu_xf_out;`
68			`input wire ctl_flags_nf_set;`
69			`input wire alu_zero;`
70			`input wire shift_cf_out;`
71			`input wire alu_core_cf_out;`
72			`input wire daa_cf_out;`
73			`input wire ctl_flags_cf_set;`
74			`input wire ctl_flags_cf_cpl;`
75			`input wire pf_sel;`
76			`input wire ctl_flags_cf_we;`
77			`input wire ctl_flags_sz_we;`
78			`input wire ctl_flags_xy_we;`
79			`input wire ctl_flags_hf_we;`
80			`input wire ctl_flags_pf_we;`
81			`input wire ctl_flags_nf_we;`
82			`input wire ctl_flags_cf2_we;`
83			`input wire ctl_flags_hf_cpl;`
84			`input wire ctl_flags_use_cf2;`
85			`input wire ctl_flags_hf2_we;`
86			`input wire ctl_flags_nf_clr;`
87			`input wire ctl_alu_zero_16bit;`
88			`input wire clk;`
89	8	gdevic	`input wire ctl_flags_cf2_sel_shift;`
90			`input wire ctl_flags_cf2_sel_daa;`
91	16	gdevic	`input wire nhold_clk_wait;`
92	3	gdevic	`output wire flags_sf;`
93			`output wire flags_zf;`
94			`output wire flags_hf;`
95			`output wire flags_pf;`
96			`output wire flags_cf;`
97			`output wire flags_nf;`
98			`output wire flags_cf_latch;`
99			`output reg flags_hf2;`
100			`inout wire [7:0] db;`
101
102			`reg flags_xf;`
103			`reg flags_yf;`
104	8	gdevic	`wire [1:0] sel;`
105	14	gdevic	`reg DFFE_inst_latch_hf;`
106	3	gdevic	`wire SYNTHESIZED_WIRE_0;`
107			`wire SYNTHESIZED_WIRE_1;`
108			`wire SYNTHESIZED_WIRE_2;`
109			`wire SYNTHESIZED_WIRE_3;`
110			`wire SYNTHESIZED_WIRE_4;`
111			`wire SYNTHESIZED_WIRE_5;`
112			`wire SYNTHESIZED_WIRE_6;`
113			`wire SYNTHESIZED_WIRE_7;`
114	16	gdevic	`reg SYNTHESIZED_WIRE_39;`
115			`wire SYNTHESIZED_WIRE_8;`
116	3	gdevic	`wire SYNTHESIZED_WIRE_9;`
117	16	gdevic	`wire SYNTHESIZED_WIRE_10;`
118	3	gdevic	`wire SYNTHESIZED_WIRE_11;`
119			`wire SYNTHESIZED_WIRE_12;`
120			`wire SYNTHESIZED_WIRE_13;`
121			`wire SYNTHESIZED_WIRE_14;`
122			`wire SYNTHESIZED_WIRE_15;`
123			`wire SYNTHESIZED_WIRE_16;`
124			`wire SYNTHESIZED_WIRE_17;`
125			`wire SYNTHESIZED_WIRE_18;`
126			`wire SYNTHESIZED_WIRE_19;`
127			`wire SYNTHESIZED_WIRE_20;`
128			`wire SYNTHESIZED_WIRE_21;`
129			`wire SYNTHESIZED_WIRE_22;`
130	16	gdevic	`reg DFFE_inst_latch_sf;`
131	14	gdevic	`wire SYNTHESIZED_WIRE_23;`
132	16	gdevic	`reg DFFE_inst_latch_pf;`
133			`reg DFFE_inst_latch_nf;`
134	14	gdevic	`wire SYNTHESIZED_WIRE_24;`
135			`wire SYNTHESIZED_WIRE_25;`
136	3	gdevic	`wire SYNTHESIZED_WIRE_26;`
137			`wire SYNTHESIZED_WIRE_27;`
138			`wire SYNTHESIZED_WIRE_28;`
139	14	gdevic	`wire SYNTHESIZED_WIRE_29;`
140	16	gdevic	`wire SYNTHESIZED_WIRE_40;`
141			`wire SYNTHESIZED_WIRE_32;`
142			`wire SYNTHESIZED_WIRE_33;`
143	3	gdevic	`wire SYNTHESIZED_WIRE_34;`
144			`wire SYNTHESIZED_WIRE_35;`
145			`wire SYNTHESIZED_WIRE_36;`
146	14	gdevic	`wire SYNTHESIZED_WIRE_37;`
147	3	gdevic	`reg DFFE_inst_latch_cf;`
148			`reg DFFE_inst_latch_cf2;`
149	16	gdevic	`wire SYNTHESIZED_WIRE_38;`
150	3	gdevic
151			`assign flags_sf = DFFE_inst_latch_sf;`
152	16	gdevic	`assign flags_zf = SYNTHESIZED_WIRE_39;`
153			`assign flags_hf = SYNTHESIZED_WIRE_23;`
154	3	gdevic	`assign flags_pf = DFFE_inst_latch_pf;`
155	16	gdevic	`assign flags_cf = SYNTHESIZED_WIRE_24;`
156	3	gdevic	`assign flags_nf = DFFE_inst_latch_nf;`
157			`assign flags_cf_latch = DFFE_inst_latch_cf;`
158	16	gdevic	`assign SYNTHESIZED_WIRE_38 = 0;`
159	3	gdevic
160
161
162	16	gdevic	`assign SYNTHESIZED_WIRE_10 = db[7] & ctl_flags_bus;`
163	3	gdevic
164	16	gdevic	`assign SYNTHESIZED_WIRE_17 = alu_xf_out & ctl_flags_alu;`
165	3	gdevic
166	16	gdevic	`assign SYNTHESIZED_WIRE_20 = db[2] & ctl_flags_bus;`
167	3	gdevic
168	16	gdevic	`assign SYNTHESIZED_WIRE_19 = pf_sel & ctl_flags_alu;`
169	3	gdevic
170	14	gdevic	`assign SYNTHESIZED_WIRE_2 = db[1] & ctl_flags_bus;`
171	3	gdevic
172	16	gdevic	`assign SYNTHESIZED_WIRE_23 = DFFE_inst_latch_hf ^ ctl_flags_hf_cpl;`
173	3	gdevic
174	16	gdevic	`assign SYNTHESIZED_WIRE_22 = db[0] & ctl_flags_bus;`
175	3	gdevic
176	16	gdevic	`assign SYNTHESIZED_WIRE_21 = ctl_flags_alu & alu_core_cf_out;`
177	3	gdevic
178	16	gdevic	`assign SYNTHESIZED_WIRE_8 = ~ctl_flags_cf2_we;`
179	3	gdevic
180	16	gdevic	`assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_0 ^ ctl_flags_cf_cpl;`
181	3	gdevic
182	14	gdevic	`assign SYNTHESIZED_WIRE_1 = alu_sf_out & ctl_flags_alu;`
183	3	gdevic
184	16	gdevic	`assign SYNTHESIZED_WIRE_9 = alu_sf_out & ctl_flags_alu;`
185	3	gdevic
186	14	gdevic	`assign SYNTHESIZED_WIRE_5 = ctl_flags_nf_set \| SYNTHESIZED_WIRE_1 \| SYNTHESIZED_WIRE_2;`
187	3	gdevic
188	16	gdevic	`assign SYNTHESIZED_WIRE_37 = SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_4;`
189	3	gdevic
190
191	16	gdevic	`assign SYNTHESIZED_WIRE_32 = SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_6;`
192	3	gdevic
193	14	gdevic	`assign SYNTHESIZED_WIRE_6 = ~ctl_flags_nf_clr;`
194	3	gdevic
195	14	gdevic	`assign SYNTHESIZED_WIRE_7 = ~ctl_alu_zero_16bit;`
196	3	gdevic
197	16	gdevic	`assign SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_7 \| SYNTHESIZED_WIRE_39;`
198	3	gdevic
199	16	gdevic	`assign SYNTHESIZED_WIRE_27 = ctl_flags_cf_we & nhold_clk_wait & SYNTHESIZED_WIRE_8;`
200	3	gdevic
201	16	gdevic	`assign SYNTHESIZED_WIRE_29 = ctl_flags_cf2_we & nhold_clk_wait;`
202	3	gdevic
203	16	gdevic	`assign SYNTHESIZED_WIRE_12 = db[6] & ctl_flags_bus;`
204	3	gdevic
205	16	gdevic	`assign SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_9 \| SYNTHESIZED_WIRE_10;`
206	3	gdevic
207	16	gdevic	`assign SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_11 \| SYNTHESIZED_WIRE_12;`
208	3	gdevic
209	16	gdevic	`assign SYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_13 \| SYNTHESIZED_WIRE_14;`
210	3	gdevic
211	16	gdevic	`assign SYNTHESIZED_WIRE_40 = SYNTHESIZED_WIRE_15 \| SYNTHESIZED_WIRE_16;`
212	3	gdevic
213	16	gdevic	`assign SYNTHESIZED_WIRE_35 = SYNTHESIZED_WIRE_17 \| SYNTHESIZED_WIRE_18;`
214	3	gdevic
215	16	gdevic	`assign SYNTHESIZED_WIRE_33 = SYNTHESIZED_WIRE_19 \| SYNTHESIZED_WIRE_20;`
216	3	gdevic
217	16	gdevic	`assign SYNTHESIZED_WIRE_11 = alu_zero & ctl_flags_alu;`
218	3	gdevic
219	16	gdevic	`assign SYNTHESIZED_WIRE_26 = SYNTHESIZED_WIRE_21 \| SYNTHESIZED_WIRE_22;`
220	14	gdevic
221	3	gdevic	`assign db[7] = ctl_flags_oe ? DFFE_inst_latch_sf : 1'bz;`
222
223	16	gdevic	`assign SYNTHESIZED_WIRE_14 = db[5] & ctl_flags_bus;`
224	3	gdevic
225	16	gdevic	`assign db[6] = ctl_flags_oe ? SYNTHESIZED_WIRE_39 : 1'bz;`
226	3	gdevic
227			`assign db[5] = ctl_flags_oe ? flags_yf : 1'bz;`
228
229	16	gdevic	`assign db[4] = ctl_flags_oe ? SYNTHESIZED_WIRE_23 : 1'bz;`
230	3	gdevic
231			`assign db[3] = ctl_flags_oe ? flags_xf : 1'bz;`
232
233			`assign db[2] = ctl_flags_oe ? DFFE_inst_latch_pf : 1'bz;`
234
235			`assign db[1] = ctl_flags_oe ? DFFE_inst_latch_nf : 1'bz;`
236
237	16	gdevic	`assign db[0] = ctl_flags_oe ? SYNTHESIZED_WIRE_24 : 1'bz;`
238	3	gdevic
239	16	gdevic	`assign SYNTHESIZED_WIRE_13 = alu_yf_out & ctl_flags_alu;`
240	3	gdevic
241	16	gdevic	`assign SYNTHESIZED_WIRE_0 = ctl_flags_cf_set \| SYNTHESIZED_WIRE_25;`
242	3	gdevic
243	16	gdevic	`assign SYNTHESIZED_WIRE_16 = db[4] & ctl_flags_bus;`
244	3	gdevic
245	16	gdevic	`assign SYNTHESIZED_WIRE_15 = alu_core_cf_out & ctl_flags_alu;`
246	3	gdevic
247	16	gdevic	`assign SYNTHESIZED_WIRE_18 = db[3] & ctl_flags_bus;`
248	3	gdevic
249
250			`always@(posedge clk)`
251			`begin`
252	16	gdevic	`if (SYNTHESIZED_WIRE_27)`
253	3	gdevic	`begin`
254	16	gdevic	`DFFE_inst_latch_cf <= SYNTHESIZED_WIRE_26;`
255	3	gdevic	`end`
256			`end`
257
258
259			`always@(posedge clk)`
260			`begin`
261	16	gdevic	`if (SYNTHESIZED_WIRE_29)`
262	3	gdevic	`begin`
263	16	gdevic	`DFFE_inst_latch_cf2 <= SYNTHESIZED_WIRE_28;`
264	3	gdevic	`end`
265			`end`
266
267
268			`always@(posedge clk)`
269			`begin`
270			`if (ctl_flags_hf_we)`
271			`begin`
272	16	gdevic	`DFFE_inst_latch_hf <= SYNTHESIZED_WIRE_40;`
273	3	gdevic	`end`
274			`end`
275
276
277			`always@(posedge clk)`
278			`begin`
279			`if (ctl_flags_hf2_we)`
280			`begin`
281	16	gdevic	`flags_hf2 <= SYNTHESIZED_WIRE_40;`
282	3	gdevic	`end`
283			`end`
284
285
286			`always@(posedge clk)`
287			`begin`
288			`if (ctl_flags_nf_we)`
289			`begin`
290	16	gdevic	`DFFE_inst_latch_nf <= SYNTHESIZED_WIRE_32;`
291	3	gdevic	`end`
292			`end`
293
294
295			`always@(posedge clk)`
296			`begin`
297			`if (ctl_flags_pf_we)`
298			`begin`
299	16	gdevic	`DFFE_inst_latch_pf <= SYNTHESIZED_WIRE_33;`
300	3	gdevic	`end`
301			`end`
302
303
304			`always@(posedge clk)`
305			`begin`
306			`if (ctl_flags_sz_we)`
307			`begin`
308	16	gdevic	`DFFE_inst_latch_sf <= SYNTHESIZED_WIRE_34;`
309	3	gdevic	`end`
310			`end`
311
312
313			`always@(posedge clk)`
314			`begin`
315			`if (ctl_flags_xy_we)`
316			`begin`
317	16	gdevic	`flags_xf <= SYNTHESIZED_WIRE_35;`
318	3	gdevic	`end`
319			`end`
320
321
322			`always@(posedge clk)`
323			`begin`
324			`if (ctl_flags_xy_we)`
325			`begin`
326	16	gdevic	`flags_yf <= SYNTHESIZED_WIRE_36;`
327	3	gdevic	`end`
328			`end`
329
330
331			`always@(posedge clk)`
332			`begin`
333			`if (ctl_flags_sz_we)`
334			`begin`
335	16	gdevic	`SYNTHESIZED_WIRE_39 <= SYNTHESIZED_WIRE_37;`
336	3	gdevic	`end`
337			`end`
338
339
340			`alu_mux_2 b2v_inst_mux_cf(`
341			`.in0(DFFE_inst_latch_cf),`
342			`.in1(DFFE_inst_latch_cf2),`
343			`.sel1(ctl_flags_use_cf2),`
344	16	gdevic	`.out(SYNTHESIZED_WIRE_25));`
345	3	gdevic
346
347			`alu_mux_4 b2v_inst_mux_cf2(`
348			`.in0(alu_core_cf_out),`
349			`.in1(shift_cf_out),`
350			`.in2(daa_cf_out),`
351	16	gdevic	`.in3(SYNTHESIZED_WIRE_38),`
352	8	gdevic	`.sel(sel),`
353	16	gdevic	`.out(SYNTHESIZED_WIRE_28));`
354	3	gdevic
355	8	gdevic	`assign sel[0] = ctl_flags_cf2_sel_shift;`
356			`assign sel[1] = ctl_flags_cf2_sel_daa;`
357	3	gdevic
358			`endmodule`

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