URL
https://opencores.org/ocsvn/a-z80/a-z80/trunk
[/] [a-z80/] [trunk/] [cpu/] [alu/] [alu_mux_2z.v] - Blame information for rev 3
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
3 |
gdevic |
// Copyright (C) 1991-2013 Altera Corporation
|
2 |
|
|
// Your use of Altera Corporation's design tools, logic functions
|
3 |
|
|
// and other software and tools, and its AMPP partner logic
|
4 |
|
|
// functions, and any output files from any of the foregoing
|
5 |
|
|
// (including device programming or simulation files), and any
|
6 |
|
|
// associated documentation or information are expressly subject
|
7 |
|
|
// to the terms and conditions of the Altera Program License
|
8 |
|
|
// Subscription Agreement, Altera MegaCore Function License
|
9 |
|
|
// Agreement, or other applicable license agreement, including,
|
10 |
|
|
// without limitation, that your use is for the sole purpose of
|
11 |
|
|
// programming logic devices manufactured by Altera and sold by
|
12 |
|
|
// Altera or its authorized distributors. Please refer to the
|
13 |
|
|
// applicable agreement for further details.
|
14 |
|
|
|
15 |
|
|
// PROGRAM "Quartus II 64-Bit"
|
16 |
|
|
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
17 |
|
|
// CREATED "Fri Oct 31 21:18:33 2014"
|
18 |
|
|
|
19 |
|
|
module alu_mux_2z(
|
20 |
|
|
sel_a,
|
21 |
|
|
sel_zero,
|
22 |
|
|
a,
|
23 |
|
|
ena,
|
24 |
|
|
Q
|
25 |
|
|
);
|
26 |
|
|
|
27 |
|
|
|
28 |
|
|
input wire sel_a;
|
29 |
|
|
input wire sel_zero;
|
30 |
|
|
input wire [3:0] a;
|
31 |
|
|
output wire ena;
|
32 |
|
|
output wire [3:0] Q;
|
33 |
|
|
|
34 |
|
|
wire [3:0] SYNTHESIZED_WIRE_0;
|
35 |
|
|
wire SYNTHESIZED_WIRE_1;
|
36 |
|
|
|
37 |
|
|
|
38 |
|
|
|
39 |
|
|
|
40 |
|
|
assign SYNTHESIZED_WIRE_0 = a & {sel_a,sel_a,sel_a,sel_a};
|
41 |
|
|
|
42 |
|
|
assign ena = sel_a | sel_zero;
|
43 |
|
|
|
44 |
|
|
assign Q = SYNTHESIZED_WIRE_0 & {SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1};
|
45 |
|
|
|
46 |
|
|
assign SYNTHESIZED_WIRE_1 = ~sel_zero;
|
47 |
|
|
|
48 |
|
|
|
49 |
|
|
endmodule
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.