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[/] [a-z80/] [trunk/] [cpu/] [bus/] [test_pins.sv] - Blame information for rev 8

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1 3 gdevic
//==============================================================
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// Test address and data pins blocks
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//==============================================================
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`timescale 1us/ 100 ns
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module test_pins;
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// ----------------- CLOCKS AND RESET -----------------
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// Define one full T-clock cycle delay
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`define T #2
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bit clk = 1;
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initial repeat (24) #1 clk = ~clk;
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// ------------------------ ADDRESS PINS ---------------------
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logic [15:0] ab;            // Internal address bus
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logic ctl_ab_we;            // Write enable to address pin latch
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logic pin_control_oe;        // Output enable to address pins; otherwise tri-stated
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wire [15:0] apin;           // Output address bus to address pins
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// ------------------------ DATA PINS ------------------------
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logic ctl_db_we;            // Write enable to data pin output latch
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logic ctl_db_oe;            // Output enable to internal data bus
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logic ctl_db_pin_re;        // Read from the data pin into the latch
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logic ctl_db_pin_oe;        // Output enable to data pins; otherwise tri-stated
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logic ctl_pin_oe;
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// ----------------------------------------------------
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// Bidirectional internal data bus
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logic  [7:0] db_w;          // Drive it using this bus
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wire [7:0] db;              // Read it using this bus
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assign db = db_w;           // Drive 3-state bidirectional bus
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always_comb                 // Output to pin bus only when our
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begin                       // test is not driving it
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    if (db_w==='z)
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        ctl_db_oe = 1;
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    else
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        ctl_db_oe = 0;
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end
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// ----------------------------------------------------
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// Bidirectional external data pins
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logic  [7:0] dpin_w;        // Drive it using this bus
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wire [7:0] dpin;            // Read it using this bus
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assign dpin = dpin_w;       // Drive 3-state bidirectional
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always_comb                 // Output to pin bus only when our
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begin                       // test is not driving it
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    if (dpin_w==='z)
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        ctl_db_pin_oe = 1;
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    else
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        ctl_db_pin_oe = 0;
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end
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// ----------------- TEST -------------------
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`define CHECKA(arg) \
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   assert(apin===arg);
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`define CHECKD(arg) \
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   assert(dpin===arg);
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initial begin
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    ab = 16'h0;
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    ctl_ab_we = 0;
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    pin_control_oe = 0;
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    db_w = 'z;
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    dpin_w = 'z;
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    ctl_db_we = 0;
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    //------------------------------------------------------------
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    // Test the address pin logic
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    `T  ab = 16'hAA55;      // Latch a value and output it
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        ctl_ab_we = 1;
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        pin_control_oe = 1;
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    `T  ctl_ab_we = 0;
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    `T `CHECKA(16'hAA55);
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        pin_control_oe = 0;
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        ab = 16'h1234;      // Should not affect
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    `T  pin_control_oe = 1;  // Toggle output on and off
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    `T `CHECKA(16'hAA55);
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        pin_control_oe = 0;
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    `T `CHECKA(16'hz);
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    //------------------------------------------------------------
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    // Test the data pin logic
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    `T  dpin_w = 8'hAA;     // Load and latch a value
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        ctl_db_pin_re = 1;  // Read into the latch
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    `T  dpin_w = 'z;
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        db_w = 8'h55;
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        ctl_db_pin_re = 0;
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        ctl_db_we = 1;
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       `CHECKD(8'hAA);
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    `T  db_w = 'z;
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    `T $display("End of test");
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end
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//--------------------------------------------------------------
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// Instantiate bus block and assign identical nets and variables
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//--------------------------------------------------------------
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address_pins address_pins_inst( .*, .bus_ab_pin_we(ctl_ab_we), .address(ab[15:0]), .abus(apin[15:0]) );
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103 8 gdevic
data_pins data_pins_inst( .*, .ctl_bus_db_oe(ctl_db_pin_oe), .ctl_bus_db_we(ctl_db_we), .bus_db_pin_oe(ctl_db_pin_oe), .bus_db_pin_re(ctl_db_pin_re), .D(dpin[7:0]) );
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endmodule

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