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[/] [a-z80/] [trunk/] [cpu/] [control/] [clk_delay.v] - Blame information for rev 16

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1 3 gdevic
// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions 
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// and other software and tools, and its AMPP partner logic 
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// functions, and any output files from any of the foregoing 
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// (including device programming or simulation files), and any 
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// associated documentation or information are expressly subject 
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// to the terms and conditions of the Altera Program License 
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// Subscription Agreement, Altera MegaCore Function License 
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// Agreement, or other applicable license agreement, including, 
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// without limitation, that your use is for the sole purpose of 
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// programming logic devices manufactured by Altera and sold by 
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// Altera or its authorized distributors.  Please refer to the 
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// applicable agreement for further details.
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// PROGRAM              "Quartus II 64-Bit"
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// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
17 16 gdevic
// CREATED              "Sat Dec 10 08:59:31 2016"
18 3 gdevic
 
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module clk_delay(
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        clk,
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        in_intr,
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        nreset,
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        T1,
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        latch_wait,
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        mwait,
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        M1,
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        busrq,
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        setM1,
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        hold_clk_iorq,
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        hold_clk_wait,
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        iorq_Tw,
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        busack,
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        pin_control_oe,
34 16 gdevic
        hold_clk_busrq,
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        nhold_clk_wait
36 3 gdevic
);
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input wire      clk;
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input wire      in_intr;
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input wire      nreset;
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input wire      T1;
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input wire      latch_wait;
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input wire      mwait;
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input wire      M1;
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input wire      busrq;
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input wire      setM1;
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output wire     hold_clk_iorq;
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output wire     hold_clk_wait;
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output wire     iorq_Tw;
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output wire     busack;
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output wire     pin_control_oe;
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output wire     hold_clk_busrq;
54 16 gdevic
output wire     nhold_clk_wait;
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reg     hold_clk_busrq_ALTERA_SYNTHESIZED;
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wire    SYNTHESIZED_WIRE_6;
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wire    SYNTHESIZED_WIRE_1;
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reg     DFF_inst5;
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reg     SYNTHESIZED_WIRE_7;
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reg     SYNTHESIZED_WIRE_8;
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wire    SYNTHESIZED_WIRE_3;
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wire    SYNTHESIZED_WIRE_4;
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wire    SYNTHESIZED_WIRE_5;
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reg     SYNTHESIZED_WIRE_9;
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67 16 gdevic
assign  hold_clk_wait = SYNTHESIZED_WIRE_9;
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assign  iorq_Tw = DFF_inst5;
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always@(posedge SYNTHESIZED_WIRE_6 or negedge nreset)
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begin
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if (!nreset)
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        begin
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        SYNTHESIZED_WIRE_9 <= 0;
78 3 gdevic
        end
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else
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if (SYNTHESIZED_WIRE_1)
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        begin
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        SYNTHESIZED_WIRE_9 <= mwait;
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        end
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end
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always@(posedge SYNTHESIZED_WIRE_6 or negedge nreset)
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begin
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if (!nreset)
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        begin
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        SYNTHESIZED_WIRE_8 <= 0;
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        end
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else
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        begin
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        SYNTHESIZED_WIRE_8 <= busrq;
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        end
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end
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assign  hold_clk_iorq = DFF_inst5 | SYNTHESIZED_WIRE_7;
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assign  busack = SYNTHESIZED_WIRE_8 & hold_clk_busrq_ALTERA_SYNTHESIZED;
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assign  pin_control_oe = SYNTHESIZED_WIRE_3 & nreset;
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assign  SYNTHESIZED_WIRE_5 = hold_clk_busrq_ALTERA_SYNTHESIZED | setM1;
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assign  SYNTHESIZED_WIRE_3 =  ~hold_clk_busrq_ALTERA_SYNTHESIZED;
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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        begin
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        SYNTHESIZED_WIRE_7 <= 0;
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        end
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else
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        begin
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        SYNTHESIZED_WIRE_7 <= SYNTHESIZED_WIRE_4;
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        end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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        begin
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        hold_clk_busrq_ALTERA_SYNTHESIZED <= 0;
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        end
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else
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if (SYNTHESIZED_WIRE_5)
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        begin
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        hold_clk_busrq_ALTERA_SYNTHESIZED <= SYNTHESIZED_WIRE_8;
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        end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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        begin
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        DFF_inst5 <= 0;
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        end
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else
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        begin
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        DFF_inst5 <= SYNTHESIZED_WIRE_7;
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        end
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end
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assign  SYNTHESIZED_WIRE_4 = in_intr & M1 & T1;
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151 16 gdevic
assign  SYNTHESIZED_WIRE_1 = latch_wait | SYNTHESIZED_WIRE_9;
152 3 gdevic
 
153 16 gdevic
assign  nhold_clk_wait =  ~SYNTHESIZED_WIRE_9;
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155 3 gdevic
assign  SYNTHESIZED_WIRE_6 =  ~clk;
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assign  hold_clk_busrq = hold_clk_busrq_ALTERA_SYNTHESIZED;
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endmodule

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