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[/] [a-z80/] [trunk/] [cpu/] [control/] [exec_matrix.vh] - Blame information for rev 7

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Line No. Rev Author Line
1 6 gdevic
// Automatically generated by genmatrix.py
2
// 8-bit Load Group
3
if (pla[17] && !pla[50]) begin
4
    if (M1 && T1) begin
5
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */
6
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
7
                    ctl_sw_2d=1;
8
                    ctl_sw_1d=1;
9
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
10
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
11
    if (M2 && T1) begin  fMRead=1;
12
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
13
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
14
    if (M2 && T2) begin  fMRead=1;
15
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
16
                    ctl_inc_cy=pc_inc; /* Increment */
17
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
18
    if (M2 && T3) begin  fMRead=1; nextM=1; setM1=1; end
19
end
20
 
21
if (pla[61] && !pla[58] && !pla[59]) begin
22
    if (M1 && T1) begin
23
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */
24
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
25
                    ctl_sw_2u=1;
26
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
27
                    ctl_alu_op1_oe=1; /* OP1 latch */ end
28
    if (M1 && T4) begin  validPLA=1; nextM=1; setM1=1;
29
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
30
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
31
                    ctl_sw_2d=1;
32
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
33
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
34
end
35
 
36
if (use_ixiy && pla[58]) begin
37
    if (M1 && T1) begin
38
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */
39
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
40
                    ctl_sw_2d=1;
41
                    ctl_sw_1d=1;
42
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
43
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
44
    if (M2 && T1) begin  fMRead=1;
45
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
46
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
47
    if (M2 && T2) begin  fMRead=1;
48
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
49
                    ctl_inc_cy=pc_inc; /* Increment */
50
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
51
    if (M2 && T3) begin  fMRead=1; nextM=1; end
52
    if (M3 && T1) begin  ixy_d=1; /* Compute WZ=IX+d */ end
53
    if (M3 && T2) begin  ixy_d=1; /* Compute WZ=IX+d */ end
54
    if (M3 && T3) begin  ixy_d=1; /* Compute WZ=IX+d */ end
55
    if (M3 && T4) begin  ixy_d=1; /* Compute WZ=IX+d */ end
56
    if (M3 && T5) begin  nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
57
end
58
 
59
if (~use_ixiy && pla[58]) begin
60
    if (M1 && T1) begin
61
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */
62
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
63
                    ctl_sw_2d=1;
64
                    ctl_sw_1d=1;
65
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
66
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
67
    if (M2 && T1) begin  fMRead=1;
68
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
69
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
70
    if (M2 && T2) begin  fMRead=1; end
71
    if (M2 && T3) begin  fMRead=1; nextM=1; setM1=1; end
72
    if (M4 && T1) begin  fMRead=1;
73
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
74
    if (M4 && T2) begin  fMRead=1; end
75
    if (M4 && T3) begin  fMRead=1; nextM=1; setM1=1; end
76
end
77
 
78
if (use_ixiy && pla[59]) begin
79
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
80
    if (M2 && T1) begin  fMRead=1;
81
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
82
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
83
    if (M2 && T2) begin  fMRead=1;
84
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
85
                    ctl_inc_cy=pc_inc; /* Increment */
86
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
87
    if (M2 && T3) begin  fMRead=1; nextM=1; end
88
    if (M3 && T1) begin  ixy_d=1; /* Compute WZ=IX+d */ end
89
    if (M3 && T2) begin  ixy_d=1; /* Compute WZ=IX+d */ end
90
    if (M3 && T3) begin  ixy_d=1; /* Compute WZ=IX+d */ end
91
    if (M3 && T4) begin  ixy_d=1; /* Compute WZ=IX+d */ end
92
    if (M3 && T5) begin  nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end
93
end
94
 
95
if (~use_ixiy && pla[59]) begin
96
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mWrite=1;
97
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
98
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
99
                    ctl_sw_2u=1;
100
                    ctl_sw_1u=1;
101
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
102
    if (M2 && T1) begin  fMWrite=1;
103
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
104
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
105
    if (M2 && T2) begin  fMWrite=1; end
106
    if (M2 && T3) begin  fMWrite=1; nextM=1; setM1=1; end
107
    if (M4 && T1) begin  fMWrite=1;
108
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
109
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
110
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
111
                    ctl_sw_2u=1;
112
                    ctl_sw_1u=1;
113
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
114
    if (M4 && T2) begin  fMWrite=1; end
115
    if (M4 && T3) begin  fMWrite=1; nextM=1; setM1=1; end
116
end
117
 
118
if (pla[40]) begin
119
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
120
    if (M2 && T1) begin  fMRead=1;
121
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
122
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
123
    if (M2 && T2) begin  fMRead=1;
124
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
125
                    ctl_inc_cy=pc_inc; /* Increment */
126
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
127
    if (M2 && T3) begin  fMRead=1; nextM=1; ctl_mRead=1; end
128
    if (M3 && T1) begin  fMRead=1;
129
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
130
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ ixy_d=1; /* Compute WZ=IX+d */ end
131
    if (M3 && T2) begin  fMRead=1;
132
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
133
                    ctl_inc_cy=pc_inc; /* Increment */
134
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ ixy_d=1; /* Compute WZ=IX+d */ end
135
    if (M3 && T3) begin  fMRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
136
    if (M3 && T4) begin  ixy_d=1; /* Compute WZ=IX+d */ end
137
    if (M3 && T5) begin  nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end
138
end
139
 
140
if (pla[50] && !pla[40]) begin
141
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
142
    if (M2 && T1) begin  fMRead=1;
143
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
144
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
145
    if (M2 && T2) begin  fMRead=1;
146
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
147
                    ctl_inc_cy=pc_inc; /* Increment */
148
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
149
    if (M2 && T3) begin  fMRead=1; nextM=1; ctl_mWrite=1; end
150
    if (M3 && T1) begin  fMWrite=1;
151
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
152
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
153
    if (M3 && T2) begin  fMWrite=1; end
154
    if (M3 && T3) begin  fMWrite=1; nextM=1; setM1=1; end
155
    if (M4 && T1) begin  fMWrite=1;
156
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
157
    if (M4 && T2) begin  fMWrite=1; end
158
    if (M4 && T3) begin  fMWrite=1; nextM=1; setM1=1; end
159
end
160
 
161
if (pla[8] && pla[13]) begin
162
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mWrite=1;
163
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
164
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
165
                    ctl_sw_2u=1;
166
                    ctl_sw_1u=1;
167
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
168
    if (M2 && T1) begin  fMWrite=1;
169
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
170
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
171
    if (M2 && T2) begin  fMWrite=1;
172
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
173
                    ctl_inc_cy=pc_inc; /* Increment */
174
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
175
    if (M2 && T3) begin  fMWrite=1; nextM=1; setM1=1; end
176
end
177
 
178
if (pla[8] && !pla[13]) begin
179
    if (M1 && T1) begin
180
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
181
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
182
                    ctl_sw_2d=1;
183
                    ctl_sw_1d=1;
184
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
185
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
186
    if (M2 && T1) begin  fMRead=1;
187
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
188
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
189
    if (M2 && T2) begin  fMRead=1;
190
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
191
                    ctl_inc_cy=pc_inc; /* Increment */
192
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
193
    if (M2 && T3) begin  fMRead=1; nextM=1; setM1=1; end
194
end
195
 
196
if (pla[38] && pla[13]) begin
197
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
198
    if (M2 && T1) begin  fMRead=1;
199
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
200
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
201
    if (M2 && T2) begin  fMRead=1;
202
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
203
                    ctl_inc_cy=pc_inc; /* Increment */
204
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
205
    if (M2 && T3) begin  fMRead=1; nextM=1; ctl_mRead=1;
206
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
207
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
208
                    ctl_sw_2d=1;
209
                    ctl_sw_1d=1;
210
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
211
    if (M3 && T1) begin  fMRead=1;
212
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
213
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
214
    if (M3 && T2) begin  fMRead=1;
215
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
216
                    ctl_inc_cy=pc_inc; /* Increment */
217
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
218
    if (M3 && T3) begin  fMRead=1; nextM=1; ctl_mWrite=1;
219
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
220
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
221
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
222
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
223
                    ctl_sw_2d=1;
224
                    ctl_sw_1d=1;
225
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
226
    if (M4 && T1) begin  fMWrite=1;
227
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
228
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
229
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
230
                    ctl_sw_2u=1;
231
                    ctl_sw_1u=1;
232
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
233
    if (M4 && T2) begin  fMWrite=1;
234
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
235
                    ctl_inc_cy=pc_inc; /* Increment */
236
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
237
    if (M4 && T3) begin  fMWrite=1; nextM=1; setM1=1; end
238
end
239
 
240
if (pla[38] && !pla[13]) begin
241
    if (M1 && T1) begin
242
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
243
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
244
                    ctl_sw_2d=1;
245
                    ctl_sw_1d=1;
246
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
247
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
248
    if (M2 && T1) begin  fMRead=1;
249
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
250
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
251
    if (M2 && T2) begin  fMRead=1;
252
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
253
                    ctl_inc_cy=pc_inc; /* Increment */
254
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
255
    if (M2 && T3) begin  fMRead=1; nextM=1; ctl_mRead=1;
256
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
257
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
258
                    ctl_sw_2d=1;
259
                    ctl_sw_1d=1;
260
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
261
    if (M3 && T1) begin  fMRead=1;
262
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
263
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
264
    if (M3 && T2) begin  fMRead=1;
265
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
266
                    ctl_inc_cy=pc_inc; /* Increment */
267
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
268
    if (M3 && T3) begin  fMRead=1; nextM=1; ctl_mRead=1;
269
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
270
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
271
                    ctl_sw_2d=1;
272
                    ctl_sw_1d=1;
273
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
274
    if (M4 && T1) begin  fMRead=1;
275
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
276
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
277
    if (M4 && T2) begin  fMRead=1;
278
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
279
                    ctl_inc_cy=pc_inc; /* Increment */
280
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
281
    if (M4 && T3) begin  fMRead=1; nextM=1; setM1=1; end
282
end
283
 
284
if (pla[83]) begin
285
    if (M1 && T1) begin
286
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
287
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
288
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
289
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
290
                    ctl_alu_res_oe=1; /* Result latch */
291
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
292
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
293
                    ctl_flags_sz_we=1;
294
                    ctl_flags_xy_we=1;
295
                    ctl_flags_hf_we=1;
296
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_IFF2;
297
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
298
    if (M1 && T2) begin
299
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
300
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
301
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
302
    if (M1 && T3) begin
303
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
304
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
305
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
306
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
307
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
308
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
309
                    ctl_flags_sz_we=1;
310
                    ctl_flags_xy_we=1;
311
                    ctl_flags_hf_we=1;
312
                    ctl_flags_pf_we=1;
313
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
314
                    ctl_flags_cf_we=1; end
315
    if (M1 && T4) begin  validPLA=1;
316
                    ctl_reg_sel_ir=1; ctl_reg_sys_hilo={!op3,op3}; ctl_sw_4u=1; /* Read either I or R based on op3 (0 or 1) */
317
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
318
                    ctl_sw_2d=1;
319
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
320
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
321
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
322
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
323
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
324
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
325
                    ctl_flags_sz_we=1;
326
                    ctl_flags_xy_we=1;
327
                    ctl_flags_hf_we=1;
328
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
329
    if (M1 && T5) begin  nextM=1; setM1=1; end
330
end
331
 
332
if (pla[57]) begin
333
    if (M1 && T3) begin
334
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
335
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
336
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
337
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
338
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
339
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
340
                    ctl_flags_sz_we=1;
341
                    ctl_flags_xy_we=1;
342
                    ctl_flags_hf_we=1;
343
                    ctl_flags_pf_we=1;
344
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
345
                    ctl_flags_cf_we=1; end
346
    if (M1 && T4) begin  validPLA=1;
347
                    ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo={!op3,op3}; ctl_sw_4d=1; /* Write either I or R based on op3 (0 or 1) */
348
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
349
                    ctl_sw_2u=1;
350
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
351
                    ctl_alu_op1_oe=1; /* OP1 latch */ end
352
    if (M1 && T5) begin  nextM=1; setM1=1; end
353
end
354
 
355
// 16-bit Load Group
356
if (pla[7]) begin
357
    if (M1 && T1) begin
358
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
359
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
360
                    ctl_sw_2d=1;
361
                    ctl_sw_1d=1;
362
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
363
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
364
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
365
    if (M2 && T1) begin  fMRead=1;
366
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
367
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
368
    if (M2 && T2) begin  fMRead=1;
369
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
370
                    ctl_inc_cy=pc_inc; /* Increment */
371
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
372
    if (M2 && T3) begin  fMRead=1; nextM=1; ctl_mRead=1; end
373
    if (M3 && T1) begin  fMRead=1;
374
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
375
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
376
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
377
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
378
                    ctl_sw_2d=1;
379
                    ctl_sw_1d=1;
380
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
381
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
382
    if (M3 && T2) begin  fMRead=1;
383
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
384
                    ctl_inc_cy=pc_inc; /* Increment */
385
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
386
    if (M3 && T3) begin  fMRead=1; nextM=1; setM1=1; end
387
end
388
 
389
if (pla[30] && pla[13]) begin
390
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
391
    if (M2 && T1) begin  fMRead=1;
392
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
393
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
394
    if (M2 && T2) begin  fMRead=1;
395
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
396
                    ctl_inc_cy=pc_inc; /* Increment */
397
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
398
    if (M2 && T3) begin  fMRead=1; nextM=1; ctl_mRead=1;
399
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
400
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
401
                    ctl_sw_2d=1;
402
                    ctl_sw_1d=1;
403
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
404
    if (M3 && T1) begin  fMRead=1;
405
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
406
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
407
    if (M3 && T2) begin  fMRead=1;
408
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
409
                    ctl_inc_cy=pc_inc; /* Increment */
410
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
411
    if (M3 && T3) begin  fMRead=1; nextM=1; ctl_mWrite=1;
412
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
413
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
414
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
415
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
416
                    ctl_sw_2d=1;
417
                    ctl_sw_1d=1;
418
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
419
    if (M4 && T1) begin  fMWrite=1;
420
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
421
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
422
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
423
                    ctl_sw_2u=1;
424
                    ctl_sw_1u=1;
425
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
426
    if (M4 && T2) begin  fMWrite=1;
427
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
428
                    ctl_inc_cy=pc_inc; /* Increment */
429
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
430
    if (M4 && T3) begin  fMWrite=1; nextM=1; ctl_mWrite=1;
431
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
432
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
433
    if (M5 && T1) begin  fMWrite=1;
434
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
435
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
436
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
437
                    ctl_sw_2u=1;
438
                    ctl_sw_1u=1;
439
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
440
    if (M5 && T2) begin  fMWrite=1;
441
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
442
                    ctl_inc_cy=pc_inc; /* Increment */
443
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
444
    if (M5 && T3) begin  fMWrite=1; nextM=1; setM1=1; end
445
end
446
 
447
if (pla[30] && !pla[13]) begin
448
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
449
    if (M2 && T1) begin  fMRead=1;
450
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
451
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
452
    if (M2 && T2) begin  fMRead=1;
453
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
454
                    ctl_inc_cy=pc_inc; /* Increment */
455
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
456
    if (M2 && T3) begin  fMRead=1; nextM=1; ctl_mRead=1;
457
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
458
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
459
                    ctl_sw_2d=1;
460
                    ctl_sw_1d=1;
461
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
462
    if (M3 && T1) begin  fMRead=1;
463
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
464
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
465
    if (M3 && T2) begin  fMRead=1;
466
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
467
                    ctl_inc_cy=pc_inc; /* Increment */
468
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
469
    if (M3 && T3) begin  fMRead=1; nextM=1; ctl_mRead=1;
470
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
471
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
472
                    ctl_sw_2d=1;
473
                    ctl_sw_1d=1;
474
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
475
    if (M4 && T1) begin  fMRead=1;
476
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
477
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
478
    if (M4 && T2) begin  fMRead=1;
479
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
480
                    ctl_inc_cy=pc_inc; /* Increment */
481
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
482
    if (M4 && T3) begin  fMRead=1; nextM=1; ctl_mRead=1;
483
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
484
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
485
                    ctl_sw_2d=1;
486
                    ctl_sw_1d=1;
487
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
488
    if (M5 && T1) begin  fMRead=1;
489
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
490
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
491
    if (M5 && T2) begin  fMRead=1;
492
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
493
                    ctl_inc_cy=pc_inc; /* Increment */
494
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
495
    if (M5 && T3) begin  fMRead=1; nextM=1; setM1=1;
496
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
497
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
498
                    ctl_sw_2d=1;
499
                    ctl_sw_1d=1;
500
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
501
end
502
 
503
if (pla[31] && pla[33]) begin
504
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
505
    if (M2 && T1) begin  fMRead=1;
506
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
507
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
508
    if (M2 && T2) begin  fMRead=1;
509
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
510
                    ctl_inc_cy=pc_inc; /* Increment */
511
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
512
    if (M2 && T3) begin  fMRead=1; nextM=1; ctl_mRead=1;
513
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
514
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
515
                    ctl_sw_2d=1;
516
                    ctl_sw_1d=1;
517
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
518
    if (M3 && T1) begin  fMRead=1;
519
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
520
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
521
    if (M3 && T2) begin  fMRead=1;
522
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
523
                    ctl_inc_cy=pc_inc; /* Increment */
524
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
525
    if (M3 && T3) begin  fMRead=1; nextM=1; ctl_mWrite=1;
526
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
527
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
528
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
529
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
530
                    ctl_sw_2d=1;
531
                    ctl_sw_1d=1;
532
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
533
    if (M4 && T1) begin  fMWrite=1;
534
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
535
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
536
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
537
                    ctl_sw_2u=1;
538
                    ctl_sw_1u=1;
539
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
540
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
541
    if (M4 && T2) begin  fMWrite=1;
542
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
543
                    ctl_inc_cy=pc_inc; /* Increment */
544
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
545
    if (M4 && T3) begin  fMWrite=1; nextM=1; ctl_mWrite=1;
546
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
547
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
548
    if (M5 && T1) begin  fMWrite=1;
549
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
550
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
551
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
552
                    ctl_sw_2u=1;
553
                    ctl_sw_1u=1;
554
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
555
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
556
    if (M5 && T2) begin  fMWrite=1;
557
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
558
                    ctl_inc_cy=pc_inc; /* Increment */
559
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
560
    if (M5 && T3) begin  fMWrite=1; nextM=1; setM1=1; end
561
end
562
 
563
if (pla[31] && !pla[33]) begin
564
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
565
    if (M2 && T1) begin  fMRead=1;
566
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
567
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
568
    if (M2 && T2) begin  fMRead=1;
569
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
570
                    ctl_inc_cy=pc_inc; /* Increment */
571
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
572
    if (M2 && T3) begin  fMRead=1; nextM=1; ctl_mRead=1;
573
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
574
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
575
                    ctl_sw_2d=1;
576
                    ctl_sw_1d=1;
577
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
578
    if (M3 && T1) begin  fMRead=1;
579
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
580
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
581
    if (M3 && T2) begin  fMRead=1;
582
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
583
                    ctl_inc_cy=pc_inc; /* Increment */
584
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
585
    if (M3 && T3) begin  fMRead=1; nextM=1; ctl_mRead=1;
586
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
587
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
588
                    ctl_sw_2d=1;
589
                    ctl_sw_1d=1;
590
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
591
    if (M4 && T1) begin  fMRead=1;
592
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
593
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
594
    if (M4 && T2) begin  fMRead=1;
595
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
596
                    ctl_inc_cy=pc_inc; /* Increment */
597
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
598
    if (M4 && T3) begin  fMRead=1; nextM=1; ctl_mRead=1;
599
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
600
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
601
                    ctl_sw_2d=1;
602
                    ctl_sw_1d=1;
603
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
604
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
605
    if (M5 && T1) begin  fMRead=1;
606
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
607
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
608
    if (M5 && T2) begin  fMRead=1;
609
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
610
                    ctl_inc_cy=pc_inc; /* Increment */
611
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
612
    if (M5 && T3) begin  fMRead=1; nextM=1; setM1=1;
613
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
614
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
615
                    ctl_sw_2d=1;
616
                    ctl_sw_1d=1;
617
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
618
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
619
end
620
 
621
if (pla[5]) begin
622
    if (M1 && T4) begin  validPLA=1;
623
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
624
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
625
    if (M1 && T5) begin
626
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
627
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
628
    if (M1 && T6) begin  nextM=1; setM1=1; end
629
end
630
 
631
if (pla[23] && pla[16]) begin
632
    if (M1 && T4) begin  validPLA=1; end
633
    if (M1 && T5) begin  nextM=1; ctl_mWrite=1;
634
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
635
                    ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
636
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
637
    if (M2 && T1) begin  fMWrite=1;
638
                    ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
639
                    ctl_apin_mux=1; /* Apin sourced from incrementer */
640
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
641
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
642
                    ctl_sw_2u=1;
643
                    ctl_sw_1u=1;
644
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
645
    if (M2 && T2) begin  fMWrite=1;
646
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
647
                    ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
648
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
649
    if (M2 && T3) begin  fMWrite=1; nextM=1; ctl_mWrite=1;
650
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
651
                    ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
652
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
653
    if (M3 && T1) begin  fMWrite=1;
654
                    ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
655
                    ctl_apin_mux=1; /* Apin sourced from incrementer */
656
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
657
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
658
                    ctl_sw_2u=1;
659
                    ctl_sw_1u=1;
660
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
661
    if (M3 && T2) begin  fMWrite=1;
662
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
663
                    ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
664
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
665
    if (M3 && T3) begin  fMWrite=1; nextM=1; setM1=1; end
666
end
667
 
668
if (pla[23] && !pla[16]) begin
669
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
670
    if (M2 && T1) begin  fMRead=1;
671
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
672
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
673
    if (M2 && T2) begin  fMRead=1;
674
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
675
                    ctl_inc_cy=pc_inc; /* Increment */
676
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
677
    if (M2 && T3) begin  fMRead=1; nextM=1; ctl_mRead=1;
678
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
679
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
680
                    ctl_sw_2d=1;
681
                    ctl_sw_1d=1;
682
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
683
    if (M3 && T1) begin  fMRead=1;
684
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
685
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
686
    if (M3 && T2) begin  fMRead=1;
687
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
688
                    ctl_inc_cy=pc_inc; /* Increment */
689
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
690
    if (M3 && T3) begin  fMRead=1; nextM=1; setM1=1;
691
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
692
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
693
                    ctl_sw_2d=1;
694
                    ctl_sw_1d=1;
695
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
696
end
697
 
698
// Exchange, Block Transfer and Search Groups
699
if (pla[2]) begin
700
    if (M1 && T2) begin
701
                    ctl_reg_ex_de_hl=1; /* EX DE,HL */ end
702
    if (M1 && T4) begin  validPLA=1; nextM=1; setM1=1; end
703
end
704
 
705
if (pla[39]) begin
706
    if (M1 && T2) begin
707
                    ctl_reg_ex_af=1; /* EX AF,AF' */ end
708
    if (M1 && T4) begin  validPLA=1; nextM=1; setM1=1; end
709
end
710
 
711
if (pla[1]) begin
712
    if (M1 && T2) begin
713
                    ctl_reg_exx=1; /* EXX */ end
714
    if (M1 && T4) begin  validPLA=1; nextM=1; setM1=1; end
715
end
716
 
717
if (pla[10]) begin
718
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
719
    if (M2 && T1) begin  fMRead=1;
720
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
721
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
722
    if (M2 && T2) begin  fMRead=1;
723
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
724
                    ctl_inc_cy=pc_inc; /* Increment */
725
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
726
    if (M2 && T3) begin  fMRead=1; nextM=1; ctl_mRead=1;
727
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
728
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
729
                    ctl_sw_2d=1;
730
                    ctl_sw_1d=1;
731
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
732
    if (M3 && T1) begin  fMRead=1;
733
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
734
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
735
    if (M3 && T2) begin  fMRead=1;
736
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
737
                    ctl_inc_cy=pc_inc; /* Increment */
738
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
739
    if (M3 && T3) begin  fMRead=1;
740
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
741
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
742
                    ctl_sw_2d=1;
743
                    ctl_sw_1d=1;
744
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
745
    if (M3 && T4) begin  nextM=1; ctl_mWrite=1;
746
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
747
                    ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
748
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
749
    if (M4 && T1) begin  fMWrite=1;
750
                    ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
751
                    ctl_apin_mux=1; /* Apin sourced from incrementer */
752
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
753
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
754
                    ctl_sw_2u=1;
755
                    ctl_sw_1u=1;
756
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
757
    if (M4 && T2) begin  fMWrite=1;
758
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
759
                    ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
760
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
761
    if (M4 && T3) begin  fMWrite=1; nextM=1; ctl_mWrite=1;
762
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
763
                    ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
764
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
765
    if (M5 && T1) begin  fMWrite=1;
766
                    ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
767
                    ctl_apin_mux=1; /* Apin sourced from incrementer */
768
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
769
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
770
                    ctl_sw_2u=1;
771
                    ctl_sw_1u=1;
772
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
773
    if (M5 && T2) begin  fMWrite=1;
774
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
775
                    ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
776
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
777
    if (M5 && T3) begin  fMWrite=1;
778
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
779
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
780
    if (M5 && T4) begin
781
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
782
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
783
    if (M5 && T5) begin  nextM=1; setM1=1; end
784
end
785
 
786
if (pla[0]) begin
787
    begin  nonRep=1; /* Non-repeating block instruction */ end
788
end
789
 
790
if (pla[12]) begin
791
    if (M1 && T1) begin
792
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
793
                    ctl_alu_res_oe=1; /* Result latch */
794
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
795
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
796
                    ctl_flags_xy_we=1;
797
                    ctl_flags_hf_we=1;
798
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP;
799
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
800
                    ctl_flags_use_cf2=1; end
801
    if (M1 && T2) begin
802
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
803
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
804
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
805
    if (M1 && T3) begin
806
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
807
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
808
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
809
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
810
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
811
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
812
                    ctl_flags_sz_we=1;
813
                    ctl_flags_xy_we=1;
814
                    ctl_flags_hf_we=1;
815
                    ctl_flags_pf_we=1;
816
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
817
                    ctl_flags_cf_we=1; end
818
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
819
    if (M2 && T1) begin  fMRead=1;
820
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
821
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
822
    if (M2 && T2) begin  fMRead=1;
823
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
824
                    ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
825
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
826
    if (M2 && T3) begin  fMRead=1; nextM=1; ctl_mWrite=1;
827
                    ctl_sw_2d=1;
828
                    ctl_sw_1d=1;
829
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
830
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
831
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
832
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
833
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
834
 
835
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
836
    if (ctl_alu_op_low) begin
837
                                                              ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
838
    end else begin
839
        ctl_alu_core_hf=1;
840
    end
841
                    ctl_flags_hf_we=1;
842
                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end
843
    if (M3 && T1) begin  fMWrite=1;
844
                    ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit DE, enable SW4 downstream */
845
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
846
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
847
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
848
                    ctl_alu_res_oe=1; /* Result latch */
849
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
850
 
851
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
852
    if (ctl_alu_op_low) begin
853
                                                              ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
854
    end else begin
855
        ctl_alu_core_hf=1;
856
    end
857
                    ctl_flags_use_cf2=1; end
858
    if (M3 && T2) begin  fMWrite=1;
859
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
860
                    ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
861
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
862
    if (M3 && T3) begin  fMWrite=1;
863
                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
864
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
865
    if (M3 && T4) begin
866
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
867
                    ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
868
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
869
                    ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end
870
    if (M3 && T5) begin  nextM=1; setM1=nonRep | !repeat_en; end
871
    if (M4 && T1) begin
872
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
873
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
874
    if (M4 && T2) begin
875
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
876
                    ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
877
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
878
    if (M4 && T3) begin
879
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
880
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
881
    if (M4 && T4) begin
882
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
883
                    ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
884
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
885
    if (M4 && T5) begin  nextM=1; setM1=1; end
886
end
887
 
888
if (pla[11]) begin
889
    if (M1 && T1) begin
890
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
891
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
892
                    ctl_alu_res_oe=1; /* Result latch */
893
                    ctl_alu_op1_sel_zero=1; /* Zero */
894
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
895
 
896
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;                                             ctl_alu_sel_op2_neg=1;
897
    if (ctl_alu_op_low) begin
898
                                                              ctl_flags_cf_set=1;
899
    end else begin
900
        ctl_alu_core_hf=1;
901
    end
902
                    ctl_flags_xy_we=1;
903
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP;
904
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
905
                    ctl_flags_use_cf2=1; end
906
    if (M1 && T2) begin
907
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
908
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
909
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
910
                    ctl_flags_hf_cpl=flags_nf; end
911
    if (M1 && T3) begin
912
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
913
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
914
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
915
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
916
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
917
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
918
                    ctl_flags_sz_we=1;
919
                    ctl_flags_xy_we=1;
920
                    ctl_flags_hf_we=1;
921
                    ctl_flags_pf_we=1;
922
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
923
                    ctl_flags_cf_we=1; end
924
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
925
    if (M2 && T1) begin  fMRead=1;
926
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
927
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
928
    if (M2 && T2) begin  fMRead=1;
929
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
930
                    ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
931
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
932
    if (M2 && T3) begin  fMRead=1; nextM=1;
933
                    ctl_sw_2d=1;
934
                    ctl_sw_1d=1;
935
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
936
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
937
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
938
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
939
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
940
 
941
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;                                             ctl_alu_sel_op2_neg=1;
942
    if (ctl_alu_op_low) begin
943
                                                              ctl_flags_cf_set=1;
944
    end else begin
945
        ctl_alu_core_hf=1;
946
    end
947
                    ctl_flags_hf_we=1;
948
                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end
949
    if (M3 && T1) begin
950
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
951
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
952
                    ctl_alu_res_oe=1; /* Result latch */
953
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
954
 
955
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;                                             ctl_alu_sel_op2_neg=1;
956
    if (ctl_alu_op_low) begin
957
                                                              ctl_flags_cf_set=1;
958
    end else begin
959
        ctl_alu_core_hf=1;
960
    end
961
                    ctl_flags_sz_we=1;
962
                    ctl_flags_use_cf2=1; end
963
    if (M3 && T3) begin
964
                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
965
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
966
    if (M3 && T4) begin
967
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
968
                    ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
969
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
970
                    ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end
971
    if (M3 && T5) begin  nextM=1; setM1=nonRep | !repeat_en | flags_zf; end
972
    if (M4 && T1) begin
973
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
974
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
975
    if (M4 && T2) begin
976
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
977
                    ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
978
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
979
    if (M4 && T3) begin
980
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
981
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
982
    if (M4 && T4) begin
983
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
984
                    ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
985
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
986
    if (M4 && T5) begin  nextM=1; setM1=1; end
987
end
988
 
989
// 8-bit Arithmetic and Logic Group
990
if (pla[65] && !pla[52]) begin
991
    if (M1 && T1) begin  /* Which register to be written is decided elsewhere */
992
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
993
                    ctl_sw_2u=1;
994
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
995
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
996
                    ctl_alu_res_oe=1; /* Result latch */
997
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
998
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
999
                    ctl_flags_sz_we=1;
1000
                    ctl_flags_cf_we=1; end
1001
    if (M1 && T2) begin
1002
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1003
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1004
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1005
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1006
                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
1007
    if (M1 && T3) begin
1008
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1009
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1010
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1011
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1012
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1013
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1014
                    ctl_flags_sz_we=1;
1015
                    ctl_flags_xy_we=1;
1016
                    ctl_flags_hf_we=1;
1017
                    ctl_flags_pf_we=1;
1018
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1019
                    ctl_flags_cf_we=1; end
1020
    if (M1 && T4) begin  validPLA=1; nextM=1; setM1=1;
1021
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
1022
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1023
                    ctl_sw_2d=1;
1024
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1025
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1026
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1027
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1028
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1029
                    ctl_flags_sz_we=1;
1030
                    ctl_flags_xy_we=1;
1031
                    ctl_flags_hf_we=1; end
1032
end
1033
 
1034
if (pla[64]) begin
1035
    if (M1 && T1) begin  /* Which register to be written is decided elsewhere */
1036
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1037
                    ctl_sw_2u=1;
1038
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1039
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1040
                    ctl_alu_res_oe=1; /* Result latch */
1041
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1042
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1043
                    ctl_flags_sz_we=1;
1044
                    ctl_flags_cf_we=1; end
1045
    if (M1 && T2) begin
1046
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1047
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1048
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1049
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1050
                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
1051
    if (M1 && T3) begin
1052
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1053
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1054
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1055
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1056
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1057
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1058
                    ctl_flags_sz_we=1;
1059
                    ctl_flags_xy_we=1;
1060
                    ctl_flags_hf_we=1;
1061
                    ctl_flags_pf_we=1;
1062
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1063
                    ctl_flags_cf_we=1; end
1064
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1;
1065
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
1066
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1067
                    ctl_sw_2d=1;
1068
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1069
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1070
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1071
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1072
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1073
                    ctl_flags_sz_we=1;
1074
                    ctl_flags_xy_we=1;
1075
                    ctl_flags_hf_we=1; end
1076
    if (M2 && T1) begin  fMRead=1;
1077
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
1078
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
1079
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ end
1080
    if (M2 && T2) begin  fMRead=1;
1081
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
1082
                    ctl_inc_cy=pc_inc; /* Increment */
1083
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1084
    if (M2 && T3) begin  fMRead=1; nextM=1; setM1=1;
1085
                    ctl_sw_2d=1;
1086
                    ctl_sw_1d=1;
1087
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1088
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1089
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1090
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1091
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1092
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1093
                    ctl_flags_sz_we=1;
1094
                    ctl_flags_xy_we=1;
1095
                    ctl_flags_hf_we=1; end
1096
end
1097
 
1098
if (use_ixiy && pla[52]) begin
1099
    if (M1 && T3) begin
1100
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1101
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1102
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1103
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1104
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1105
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1106
                    ctl_flags_sz_we=1;
1107
                    ctl_flags_xy_we=1;
1108
                    ctl_flags_hf_we=1;
1109
                    ctl_flags_pf_we=1;
1110
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1111
                    ctl_flags_cf_we=1; end
1112
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
1113
    if (M2 && T1) begin  fMRead=1;
1114
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
1115
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
1116
    if (M2 && T2) begin  fMRead=1;
1117
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
1118
                    ctl_inc_cy=pc_inc; /* Increment */
1119
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1120
    if (M2 && T3) begin  fMRead=1; nextM=1; end
1121
    if (M3 && T1) begin  ixy_d=1; /* Compute WZ=IX+d */ end
1122
    if (M3 && T2) begin  ixy_d=1; /* Compute WZ=IX+d */ end
1123
    if (M3 && T3) begin  ixy_d=1; /* Compute WZ=IX+d */ end
1124
    if (M3 && T4) begin  ixy_d=1; /* Compute WZ=IX+d */ end
1125
    if (M3 && T5) begin  nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
1126
end
1127
 
1128
if (!use_ixiy && pla[52]) begin
1129
    if (M1 && T1) begin  /* Which register to be written is decided elsewhere */
1130
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1131
                    ctl_sw_2u=1;
1132
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1133
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1134
                    ctl_alu_res_oe=1; /* Result latch */
1135
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1136
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1137
                    ctl_flags_sz_we=1;
1138
                    ctl_flags_cf_we=1; end
1139
    if (M1 && T2) begin
1140
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1141
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1142
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1143
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1144
                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
1145
    if (M1 && T3) begin
1146
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1147
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1148
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1149
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1150
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1151
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1152
                    ctl_flags_sz_we=1;
1153
                    ctl_flags_xy_we=1;
1154
                    ctl_flags_hf_we=1;
1155
                    ctl_flags_pf_we=1;
1156
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1157
                    ctl_flags_cf_we=1; end
1158
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
1159
    if (M2 && T1) begin  fMRead=1;
1160
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
1161
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
1162
    if (M2 && T2) begin  fMRead=1;
1163
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
1164
                    ctl_inc_cy=pc_inc; /* Increment */
1165
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1166
    if (M2 && T3) begin  fMRead=1; nextM=1; setM1=1;
1167
                    ctl_sw_2d=1;
1168
                    ctl_sw_1d=1;
1169
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1170
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1171
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1172
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1173
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1174
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1175
                    ctl_flags_sz_we=1;
1176
                    ctl_flags_xy_we=1;
1177
                    ctl_flags_hf_we=1; end
1178
    if (M4 && T1) begin  fMRead=1;
1179
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1180
    if (M4 && T2) begin  fMRead=1;
1181
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1182
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1183
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1184
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1185
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1186
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1187
                    ctl_flags_sz_we=1;
1188
                    ctl_flags_xy_we=1;
1189
                    ctl_flags_hf_we=1;
1190
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1191
                    ctl_flags_cf_we=1; end
1192
    if (M4 && T3) begin  fMRead=1; nextM=1; setM1=1;
1193
                    ctl_sw_2d=1;
1194
                    ctl_sw_1d=1;
1195
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1196
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1197
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1198
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1199
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1200
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1201
                    ctl_flags_sz_we=1;
1202
                    ctl_flags_xy_we=1;
1203
                    ctl_flags_hf_we=1; end
1204
end
1205
 
1206
if (pla[66] && !pla[53]) begin
1207
    if (M1 && T1) begin
1208
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */
1209
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1210
                    ctl_sw_2u=1;
1211
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1212
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1213
                    ctl_alu_res_oe=1; /* Result latch */
1214
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1215
 
1216
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
1217
    if (!ctl_alu_op_low) begin
1218
        ctl_alu_core_hf=1;
1219
    end
1220
                    ctl_flags_sz_we=1;
1221
                    ctl_flags_xy_we=1;
1222
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
1223
                    ctl_flags_use_cf2=1; end
1224
    if (M1 && T2) begin
1225
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1226
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1227
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1228
                    ctl_flags_hf_cpl=flags_nf; end
1229
    if (M1 && T3) begin
1230
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1231
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1232
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1233
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1234
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1235
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1236
                    ctl_flags_sz_we=1;
1237
                    ctl_flags_xy_we=1;
1238
                    ctl_flags_hf_we=1;
1239
                    ctl_flags_pf_we=1;
1240
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1241
                    ctl_flags_cf_we=1; end
1242
    if (M1 && T4) begin  validPLA=1; nextM=1; setM1=1;
1243
    if (op4 & op5 & !op3) ctl_bus_zero_oe=1;                /* Trying to read flags? Put 0 on the bus instead. */
1244
    else begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; end /* Read 8-bit GP register */
1245
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1246
                    ctl_sw_2d=1;
1247
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1248
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1249
                    ctl_alu_op2_sel_zero=1; /* Zero */
1250
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1251
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1252
 
1253
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
1254
    if (!ctl_alu_op_low) begin
1255
        ctl_alu_core_hf=1;
1256
    end
1257
                    ctl_flags_sz_we=1;
1258
                    ctl_flags_xy_we=1;
1259
                    ctl_flags_hf_we=1;
1260
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1261
                    ctl_flags_cf_set=1; /* Set CF going into the ALU core */
1262
                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end
1263
end
1264
 
1265
if (pla[75]) begin
1266
    if (M1 && T1) begin
1267
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1268
                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */
1269
                    ctl_alu_sel_op2_neg=1; end
1270
    if (M1 && T4) begin
1271
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1272
                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */
1273
                    ctl_alu_sel_op2_neg=1; end
1274
end
1275
 
1276
if ((M2 || M4) && pla[75]) begin
1277
    begin
1278
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1279
                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */
1280
                    ctl_alu_sel_op2_neg=1; end
1281
end
1282
 
1283
if (use_ixiy && pla[53]) begin
1284
    if (M1 && T3) begin
1285
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1286
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1287
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1288
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1289
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1290
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1291
                    ctl_flags_sz_we=1;
1292
                    ctl_flags_xy_we=1;
1293
                    ctl_flags_hf_we=1;
1294
                    ctl_flags_pf_we=1;
1295
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1296
                    ctl_flags_cf_we=1; end
1297
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
1298
    if (M2 && T1) begin  fMRead=1;
1299
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
1300
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
1301
    if (M2 && T2) begin  fMRead=1;
1302
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
1303
                    ctl_inc_cy=pc_inc; /* Increment */
1304
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1305
    if (M2 && T3) begin  fMRead=1; nextM=1; end
1306
    if (M3 && T1) begin  ixy_d=1; /* Compute WZ=IX+d */ end
1307
    if (M3 && T2) begin  ixy_d=1; /* Compute WZ=IX+d */ end
1308
    if (M3 && T3) begin  ixy_d=1; /* Compute WZ=IX+d */ end
1309
    if (M3 && T4) begin  ixy_d=1; /* Compute WZ=IX+d */ end
1310
    if (M3 && T5) begin  nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
1311
end
1312
 
1313
if (!use_ixiy && pla[53]) begin
1314
    if (M1 && T2) begin
1315
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1316
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1317
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1318
                    ctl_flags_hf_cpl=flags_nf; end
1319
    if (M1 && T3) begin
1320
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1321
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1322
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1323
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1324
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1325
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1326
                    ctl_flags_sz_we=1;
1327
                    ctl_flags_xy_we=1;
1328
                    ctl_flags_hf_we=1;
1329
                    ctl_flags_pf_we=1;
1330
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1331
                    ctl_flags_cf_we=1; end
1332
    if (M1 && T4) begin  validPLA=1; nextM=1; ctl_mRead=1; end
1333
    if (M2 && T1) begin  fMRead=1;
1334
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
1335
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
1336
    if (M2 && T2) begin  fMRead=1; end
1337
    if (M2 && T3) begin  fMRead=1;
1338
                    ctl_sw_2d=1;
1339
                    ctl_sw_1d=1;
1340
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1341
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1342
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1343
                    ctl_alu_op2_sel_zero=1; /* Zero */
1344
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1345
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1346
 
1347
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
1348
    if (!ctl_alu_op_low) begin
1349
        ctl_alu_core_hf=1;
1350
    end
1351
                    ctl_flags_hf_we=1;
1352
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1353
                    ctl_flags_cf_set=1; /* Set CF going into the ALU core */
1354
                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end
1355
    if (M2 && T4) begin  nextM=1; ctl_mWrite=1;
1356
                    ctl_sw_2u=1;
1357
                    ctl_sw_1u=1;
1358
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
1359
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1360
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1361
                    ctl_alu_res_oe=1; /* Result latch */
1362
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1363
 
1364
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
1365
    if (!ctl_alu_op_low) begin
1366
        ctl_alu_core_hf=1;
1367
    end
1368
                    ctl_flags_sz_we=1;
1369
                    ctl_flags_xy_we=1;
1370
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
1371
                    ctl_flags_use_cf2=1; end
1372
    if (M3 && T1) begin  fMWrite=1;
1373
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1374
    if (M3 && T2) begin  fMWrite=1; end
1375
    if (M3 && T3) begin  fMWrite=1; nextM=1; setM1=1; end
1376
    if (M4 && T1) begin  fMRead=1;
1377
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1378
    if (M4 && T2) begin  fMRead=1; end
1379
    if (M4 && T3) begin  fMRead=1;
1380
                    ctl_sw_2d=1;
1381
                    ctl_sw_1d=1;
1382
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1383
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1384
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1385
                    ctl_alu_op2_sel_zero=1; /* Zero */
1386
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1387
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1388
 
1389
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
1390
    if (!ctl_alu_op_low) begin
1391
        ctl_alu_core_hf=1;
1392
    end
1393
                    ctl_flags_hf_we=1;
1394
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1395
                    ctl_flags_cf_set=1; /* Set CF going into the ALU core */
1396
                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end
1397
    if (M4 && T4) begin  nextM=1; ctl_mWrite=1;
1398
                    ctl_sw_2u=1;
1399
                    ctl_sw_1u=1;
1400
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
1401
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1402
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1403
                    ctl_alu_res_oe=1; /* Result latch */
1404
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1405
 
1406
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
1407
    if (!ctl_alu_op_low) begin
1408
        ctl_alu_core_hf=1;
1409
    end
1410
                    ctl_flags_sz_we=1;
1411
                    ctl_flags_xy_we=1;
1412
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
1413
                    ctl_flags_use_cf2=1; end
1414
    if (M5 && T1) begin  fMWrite=1;
1415
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1416
    if (M5 && T2) begin  fMWrite=1; end
1417
    if (M5 && T3) begin  fMWrite=1; nextM=1; setM1=1; end
1418
end
1419
 
1420
// 16-bit Arithmetic Group
1421
if (pla[69]) begin
1422
    if (M1 && T2) begin
1423
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1424
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1425
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
1426
    if (M1 && T3) begin
1427
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1428
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1429
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1430
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1431
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1432
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1433
                    ctl_flags_sz_we=1;
1434
                    ctl_flags_xy_we=1;
1435
                    ctl_flags_hf_we=1;
1436
                    ctl_flags_pf_we=1;
1437
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1438
                    ctl_flags_cf_we=1; end
1439
    if (M1 && T4) begin  validPLA=1; nextM=1;
1440
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
1441
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1442
                    ctl_sw_2d=1;
1443
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1444
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
1445
    if (M2 && T1) begin
1446
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
1447
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1448
                    ctl_sw_2d=1;
1449
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1450
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1451
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1452
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1453
 
1454
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
1455
    if (ctl_alu_op_low) begin
1456
                                                              ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1457
    end else begin
1458
        ctl_alu_core_hf=1;
1459
    end
1460
                    ctl_flags_hf_we=1;
1461
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1462
    if (M2 && T2) begin
1463
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
1464
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
1465
                    ctl_sw_2u=1;
1466
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1467
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1468
                    ctl_alu_res_oe=1; /* Result latch */
1469
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1470
 
1471
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
1472
    if (!ctl_alu_op_low) begin
1473
        ctl_alu_core_hf=1;
1474
    end
1475
                    ctl_flags_xy_we=1;
1476
                    ctl_flags_cf_we=1; end
1477
    if (M2 && T3) begin
1478
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
1479
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1480
                    ctl_sw_2d=1;
1481
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1482
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
1483
    if (M2 && T4) begin  nextM=1;
1484
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
1485
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1486
                    ctl_sw_2d=1;
1487
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1488
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1489
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1490
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1491
 
1492
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
1493
    if (!ctl_alu_op_low) begin
1494
        ctl_alu_core_hf=1;
1495
    end
1496
                    ctl_flags_hf_we=1;
1497
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1498
    if (M3 && T1) begin
1499
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
1500
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
1501
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
1502
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
1503
                    ctl_sw_2u=1;
1504
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1505
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1506
                    ctl_alu_res_oe=1; /* Result latch */
1507
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1508
 
1509
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
1510
    if (!ctl_alu_op_low) begin
1511
        ctl_alu_core_hf=1;
1512
    end
1513
                    ctl_flags_xy_we=1;
1514
                    ctl_flags_cf_we=1; end
1515
    if (M3 && T2) begin
1516
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
1517
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1518
    if (M3 && T3) begin  nextM=1; setM1=1; end
1519
end
1520
 
1521
if (op3 && pla[68]) begin
1522
    if (M1 && T2) begin
1523
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1524
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1525
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
1526
    if (M1 && T3) begin
1527
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1528
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1529
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1530
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1531
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1532
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1533
                    ctl_flags_sz_we=1;
1534
                    ctl_flags_xy_we=1;
1535
                    ctl_flags_hf_we=1;
1536
                    ctl_flags_pf_we=1;
1537
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1538
                    ctl_flags_cf_we=1; end
1539
    if (M1 && T4) begin  validPLA=1; nextM=1;
1540
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
1541
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1542
                    ctl_sw_2d=1;
1543
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1544
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
1545
    if (M2 && T1) begin
1546
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
1547
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1548
                    ctl_sw_2d=1;
1549
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1550
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1551
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1552
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1553
 
1554
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
1555
    if (!ctl_alu_op_low) begin
1556
        ctl_alu_core_hf=1;
1557
    end
1558
                    ctl_flags_hf_we=1;
1559
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1560
    if (M2 && T2) begin
1561
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
1562
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
1563
                    ctl_sw_2u=1;
1564
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1565
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1566
                    ctl_alu_res_oe=1; /* Result latch */
1567
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1568
 
1569
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
1570
    if (!ctl_alu_op_low) begin
1571
        ctl_alu_core_hf=1;
1572
    end
1573
                    ctl_flags_sz_we=1;
1574
                    ctl_flags_xy_we=1;
1575
                    ctl_flags_cf_we=1; end
1576
    if (M2 && T3) begin
1577
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
1578
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1579
                    ctl_sw_2d=1;
1580
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1581
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
1582
    if (M2 && T4) begin  nextM=1;
1583
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
1584
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1585
                    ctl_sw_2d=1;
1586
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1587
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1588
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1589
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1590
 
1591
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
1592
    if (!ctl_alu_op_low) begin
1593
        ctl_alu_core_hf=1;
1594
    end
1595
                    ctl_flags_hf_we=1;
1596
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1597
    if (M3 && T1) begin
1598
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
1599
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
1600
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
1601
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
1602
                    ctl_sw_2u=1;
1603
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1604
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1605
                    ctl_alu_res_oe=1; /* Result latch */
1606
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1607
 
1608
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
1609
    if (!ctl_alu_op_low) begin
1610
        ctl_alu_core_hf=1;
1611
    end
1612
                    ctl_flags_sz_we=1;
1613
                    ctl_flags_xy_we=1;
1614
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
1615
                    ctl_flags_cf_we=1;
1616
                    ctl_alu_zero_16bit=1; /* 16-bit arithmetic operation uses ZF calculated over 2 bytes */ end
1617
    if (M3 && T2) begin
1618
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
1619
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1620
    if (M3 && T3) begin  nextM=1; setM1=1; end
1621
end
1622
 
1623
if (!op3 && pla[68]) begin
1624
    if (M1 && T2) begin
1625
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1626
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1627
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1628
                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
1629
    if (M1 && T3) begin
1630
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1631
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1632
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1633
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1634
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1635
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1636
                    ctl_flags_sz_we=1;
1637
                    ctl_flags_xy_we=1;
1638
                    ctl_flags_hf_we=1;
1639
                    ctl_flags_pf_we=1;
1640
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1641
                    ctl_flags_cf_we=1; end
1642
    if (M1 && T4) begin  validPLA=1; nextM=1;
1643
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
1644
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1645
                    ctl_sw_2d=1;
1646
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1647
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
1648
    if (M2 && T1) begin
1649
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
1650
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1651
                    ctl_sw_2d=1;
1652
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1653
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1654
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1655
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1656
 
1657
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;                                             ctl_alu_sel_op2_neg=1;
1658
    if (ctl_alu_op_low) begin
1659
                                                                                  ctl_flags_cf_cpl=1;
1660
    end else begin
1661
        ctl_alu_core_hf=1;
1662
    end
1663
                    ctl_flags_hf_we=1;
1664
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1665
    if (M2 && T2) begin
1666
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
1667
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
1668
                    ctl_sw_2u=1;
1669
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1670
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1671
                    ctl_alu_res_oe=1; /* Result latch */
1672
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1673
 
1674
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;                                             ctl_alu_sel_op2_neg=1;
1675
    if (ctl_alu_op_low) begin
1676
                                                                                  ctl_flags_cf_cpl=1;
1677
    end else begin
1678
        ctl_alu_core_hf=1;
1679
    end
1680
                    ctl_flags_sz_we=1;
1681
                    ctl_flags_xy_we=1;
1682
                    ctl_flags_cf_we=1; end
1683
    if (M2 && T3) begin
1684
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
1685
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1686
                    ctl_sw_2d=1;
1687
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1688
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
1689
    if (M2 && T4) begin  nextM=1;
1690
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
1691
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1692
                    ctl_sw_2d=1;
1693
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1694
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1695
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1696
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1697
 
1698
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;                                             ctl_alu_sel_op2_neg=1;
1699
    if (!ctl_alu_op_low) begin
1700
        ctl_alu_core_hf=1;
1701
    end
1702
                    ctl_flags_hf_we=1;
1703
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1704
    if (M3 && T1) begin
1705
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
1706
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
1707
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
1708
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
1709
                    ctl_sw_2u=1;
1710
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1711
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1712
                    ctl_alu_res_oe=1; /* Result latch */
1713
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1714
 
1715
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;                                             ctl_alu_sel_op2_neg=1;
1716
    if (ctl_alu_op_low) begin
1717
                                                                                  ctl_flags_cf_cpl=1;
1718
    end else begin
1719
        ctl_alu_core_hf=1;
1720
    end
1721
                    ctl_flags_sz_we=1;
1722
                    ctl_flags_xy_we=1;
1723
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
1724
                    ctl_flags_cf_we=1;
1725
                    ctl_alu_zero_16bit=1; /* 16-bit arithmetic operation uses ZF calculated over 2 bytes */ end
1726
    if (M3 && T2) begin
1727
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
1728
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1729
    if (M3 && T3) begin  nextM=1; setM1=1; end
1730
end
1731
 
1732
if (pla[9]) begin
1733
    if (M1 && T4) begin  validPLA=1;
1734
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
1735
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
1736
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1737
    if (M1 && T5) begin
1738
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit general purpose register, enable SW4 upstream */
1739
                    ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
1740
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
1741
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1742
    if (M1 && T6) begin  nextM=1; setM1=1; end
1743
end
1744
 
1745
// General Purpose Arithmetic and CPU Control Groups
1746
if (pla[77]) begin
1747
    if (M1 && T1) begin
1748
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
1749
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1750
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1751
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1752
                    ctl_alu_res_oe=1; /* Result latch */
1753
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1754
 
1755
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
1756
    if (!ctl_alu_op_low) begin
1757
        ctl_alu_core_hf=1;
1758
    end
1759
                    ctl_flags_sz_we=1;
1760
                    ctl_flags_xy_we=1;
1761
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
1762
                    ctl_flags_cf_we=1;
1763
                    ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=!flags_nf; end
1764
    if (M1 && T2) begin
1765
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1766
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1767
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1768
                    ctl_flags_use_cf2=1;
1769
                    ctl_flags_hf_cpl=flags_nf; end
1770
    if (M1 && T3) begin
1771
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1772
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1773
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1774
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1775
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1776
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1777
                    ctl_flags_sz_we=1;
1778
                    ctl_flags_xy_we=1;
1779
                    ctl_flags_hf2_we=1; /* Write HF2 flag (DAA only) */
1780
                    ctl_flags_pf_we=1;
1781
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1782
                    ctl_flags_cf_we=1; end
1783
    if (M1 && T4) begin  validPLA=1; nextM=1; setM1=1;
1784
                    ctl_sw_2d=1;
1785
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1786
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1787
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1788
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1789
 
1790
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
1791
    if (!ctl_alu_op_low) begin
1792
        ctl_alu_core_hf=1;
1793
    end
1794
                    ctl_flags_sz_we=1;
1795
                    ctl_flags_xy_we=1;
1796
                    ctl_flags_hf_we=1;
1797
                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */
1798
                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel=2;
1799
                    ctl_daa_oe=1; /* Write DAA correction factor to the bus */
1800
                    ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=!flags_nf; end
1801
end
1802
 
1803
if (pla[81]) begin
1804
    if (M1 && T1) begin
1805
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
1806
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1807
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1808
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1809
                    ctl_alu_res_oe=1; /* Result latch */
1810
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1811
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1812
                    ctl_flags_xy_we=1;
1813
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1814
                    ctl_alu_sel_op2_neg=1; end
1815
    if (M1 && T2) begin
1816
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1817
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1818
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1819
                    ctl_flags_hf_cpl=flags_nf; end
1820
    if (M1 && T3) begin
1821
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1822
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1823
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1824
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1825
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1826
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1827
                    ctl_flags_sz_we=1;
1828
                    ctl_flags_xy_we=1;
1829
                    ctl_flags_hf_we=1;
1830
                    ctl_flags_pf_we=1;
1831
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1832
                    ctl_flags_cf_we=1; end
1833
    if (M1 && T4) begin  validPLA=1; nextM=1; setM1=1;
1834
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1835
                    ctl_alu_op1_sel_zero=1; /* Zero */
1836
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1837
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1838
                    ctl_flags_xy_we=1;
1839
                    ctl_flags_hf_we=1;
1840
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1841
                    ctl_alu_sel_op2_neg=1; end
1842
end
1843
 
1844
if (pla[82]) begin
1845
    if (M1 && T1) begin
1846
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
1847
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1848
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1849
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1850
                    ctl_alu_res_oe=1; /* Result latch */
1851
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1852
 
1853
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;                                             ctl_alu_sel_op2_neg=1;
1854
    if (ctl_alu_op_low) begin
1855
                                                              ctl_flags_cf_set=1;
1856
    end else begin
1857
        ctl_alu_core_hf=1;
1858
    end
1859
                    ctl_flags_sz_we=1;
1860
                    ctl_flags_xy_we=1;
1861
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
1862
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1863
                    ctl_flags_cf_we=1; end
1864
    if (M1 && T2) begin
1865
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1866
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1867
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1868
                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
1869
    if (M1 && T3) begin
1870
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1871
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1872
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1873
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1874
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1875
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1876
                    ctl_flags_sz_we=1;
1877
                    ctl_flags_xy_we=1;
1878
                    ctl_flags_hf_we=1;
1879
                    ctl_flags_pf_we=1;
1880
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1881
                    ctl_flags_cf_we=1; end
1882
    if (M1 && T4) begin  validPLA=1; nextM=1; setM1=1;
1883
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1884
                    ctl_alu_op1_sel_zero=1; /* Zero */
1885
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1886
 
1887
    ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;                                             ctl_alu_sel_op2_neg=1;
1888
    if (ctl_alu_op_low) begin
1889
                                                              ctl_flags_cf_set=1;
1890
    end else begin
1891
        ctl_alu_core_hf=1;
1892
    end
1893
                    ctl_flags_sz_we=1;
1894
                    ctl_flags_xy_we=1;
1895
                    ctl_flags_hf_we=1;
1896
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1897
                    ctl_flags_cf_we=1; end
1898
end
1899
 
1900
if (pla[89]) begin
1901
    if (M1 && T1) begin
1902
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1903
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1904
                    ctl_alu_res_oe=1; /* Result latch */
1905
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1906
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1907
                    ctl_flags_xy_we=1;
1908
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
1909
    if (M1 && T2) begin
1910
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1911
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1912
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1913
                    ctl_flags_cf_we=1; ctl_flags_cf_cpl=1; /* CCF */
1914
                    ctl_flags_hf_cpl=!flags_cf; /* Used for CCF */ end
1915
    if (M1 && T3) begin
1916
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1917
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1918
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1919
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1920
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1921
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1922
                    ctl_flags_sz_we=1;
1923
                    ctl_flags_xy_we=1;
1924
                    ctl_flags_hf_we=1;
1925
                    ctl_flags_pf_we=1;
1926
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1927
                    ctl_flags_cf_we=1; end
1928
    if (M1 && T4) begin  validPLA=1; nextM=1; setM1=1;
1929
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1930
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1931
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1932
                    ctl_flags_xy_we=1;
1933
                    ctl_flags_hf_we=1;
1934
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
1935
end
1936
 
1937
if (pla[92]) begin
1938
    if (M1 && T1) begin
1939
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1940
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1941
                    ctl_alu_res_oe=1; /* Result latch */
1942
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1943
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1944
                    ctl_flags_xy_we=1;
1945
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
1946
    if (M1 && T2) begin
1947
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1948
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1949
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1950
                    ctl_flags_cf_set=1; /* Set CF going into the ALU core */ end
1951
    if (M1 && T3) begin
1952
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1953
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
1954
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1955
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1956
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1957
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1958
                    ctl_flags_sz_we=1;
1959
                    ctl_flags_xy_we=1;
1960
                    ctl_flags_hf_we=1;
1961
                    ctl_flags_pf_we=1;
1962
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1963
                    ctl_flags_cf_we=1; end
1964
    if (M1 && T4) begin  validPLA=1; nextM=1; setM1=1;
1965
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1966
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1967
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1968
                    ctl_flags_xy_we=1;
1969
                    ctl_flags_hf_we=1;
1970
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
1971
end
1972
 
1973
if (pla[95]) begin
1974
    if (M1 && T3) begin
1975
                    ctl_state_halt_set=1; /* Enter HALT state */ end
1976
    if (M1 && T4) begin  validPLA=1; nextM=1; setM1=1; end
1977
end
1978
 
1979
if (pla[97]) begin
1980
    if (M1 && T3) begin
1981
                    ctl_iffx_bit=op3; ctl_iffx_we=1; /* DI/EI */ end
1982
    if (M1 && T4) begin  validPLA=1; nextM=1; setM1=1;
1983
                    ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
1984
end
1985
 
1986
if (pla[96]) begin
1987
    if (M1 && T3) begin
1988
                    ctl_sw_1d=1;
1989
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1990
                    ctl_im_we=1; /* IM n ('n' is read by opcode[4:3]) */ end
1991
    if (M1 && T4) begin  validPLA=1; nextM=1; setM1=1; end
1992
end
1993
 
1994
// Rotate and Shift Group
1995
if (pla[25]) begin
1996
    if (M1 && T1) begin
1997
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
1998
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1999
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2000
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2001
                    ctl_alu_res_oe=1; /* Result latch */
2002
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2003
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2004
                    ctl_flags_xy_we=1;
2005
                    ctl_flags_hf_we=1;
2006
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
2007
                    ctl_flags_cf_we=1; end
2008
    if (M1 && T2) begin
2009
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
2010
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2011
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
2012
                    ctl_flags_use_cf2=1; end
2013
    if (M1 && T3) begin
2014
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
2015
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
2016
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
2017
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2018
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2019
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2020
                    ctl_flags_sz_we=1;
2021
                    ctl_flags_xy_we=1;
2022
                    ctl_flags_hf_we=1;
2023
                    ctl_flags_pf_we=1;
2024
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
2025
                    ctl_flags_cf_we=1; end
2026
    if (M1 && T4) begin  validPLA=1; nextM=1; setM1=1;
2027
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
2028
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
2029
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2030
                    ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */
2031
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2032
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2033
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2034
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2035
                    ctl_flags_xy_we=1;
2036
                    ctl_flags_hf_we=1;
2037
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
2038
                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end
2039
end
2040
 
2041
if (~use_ixiy && pla[70] && !pla[55]) begin
2042
    if (M1 && T1) begin
2043
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */
2044
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2045
                    ctl_sw_2u=1;
2046
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2047
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
2048
                    ctl_alu_res_oe=1; /* Result latch */
2049
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
2050
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2051
                    ctl_flags_sz_we=1;
2052
                    ctl_flags_xy_we=1;
2053
                    ctl_flags_hf_we=1;
2054
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
2055
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
2056
                    ctl_flags_cf_we=1; end
2057
    if (M1 && T2) begin
2058
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
2059
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
2060
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
2061
                    ctl_flags_use_cf2=1; end
2062
    if (M1 && T3) begin
2063
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
2064
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
2065
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
2066
                    ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
2067
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2068
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2069
                    ctl_flags_sz_we=1;
2070
                    ctl_flags_xy_we=1;
2071
                    ctl_flags_hf_we=1;
2072
                    ctl_flags_pf_we=1;
2073
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
2074
                    ctl_flags_cf_we=1; end
2075
    if (M1 && T4) begin  validPLA=1; nextM=1; setM1=1;
2076
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
2077
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
2078
                    ctl_sw_2d=1;
2079
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2080
                    ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */
2081
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2082
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2083
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2084
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2085
                    ctl_flags_sz_we=1;
2086
                    ctl_flags_xy_we=1;
2087
                    ctl_flags_hf_we=1;
2088
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
2089
                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end
2090
    if (M4 && T1) begin  fMRead=1;
2091
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
2092
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
2093
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2094
                    ctl_ir_we=1; end
2095
    if (M4 && T2) begin  fMRead=1; end
2096
    if (M4 && T3) begin  fMRead=1; nextM=1; ctl_mWrite=1;
2097
                    ctl_sw_2d=1;
2098
                    ctl_sw_1d=1;
2099
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
2100
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
2101
                    ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */
2102
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
2103
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
2104
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
2105
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
2106
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
2107
                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end
2108
    if (M5 && T1) begin  fMWrite=1;
2109
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
2110
                    ctl_sw_2u=1;
2111
                    ctl_sw_1u=1;
2112
                    ctl_bus_db_we=1;<