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[/] [a-z80/] [trunk/] [cpu/] [control/] [exec_matrix.vh] - Blame information for rev 8

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Line No. Rev Author Line
1 6 gdevic
// Automatically generated by genmatrix.py
2 8 gdevic
 
3 6 gdevic
// 8-bit Load Group
4 8 gdevic
if (pla[17] & ~pla[50]) begin
5
    if (M1 & T1) begin
6
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
7 6 gdevic
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
8
                    ctl_sw_2d=1;
9
                    ctl_sw_1d=1;
10
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
11 8 gdevic
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
12
    if (M2 & T1) begin fMRead=1;
13 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
14
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
15 8 gdevic
    if (M2 & T2) begin fMRead=1;
16
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
17
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
18 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
19 8 gdevic
    if (M2 & T3) begin fMRead=1; setM1=1; end
20 6 gdevic
end
21
 
22 8 gdevic
if (pla[61] & ~pla[58] & ~pla[59]) begin
23
    if (M1 & T1) begin
24
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
25 6 gdevic
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
26
                    ctl_sw_2u=1;
27
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
28
                    ctl_alu_op1_oe=1; /* OP1 latch */ end
29 8 gdevic
    if (M1 & T4) begin validPLA=1; setM1=1;
30
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
31
                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
32
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
33 6 gdevic
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
34
end
35
 
36 8 gdevic
if (use_ixiy & pla[58]) begin
37
    if (M1 & T1) begin
38
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
39 6 gdevic
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
40
                    ctl_sw_2d=1;
41
                    ctl_sw_1d=1;
42
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
43 8 gdevic
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
44
    if (M2 & T1) begin fMRead=1;
45 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
46
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
47 8 gdevic
    if (M2 & T2) begin fMRead=1;
48
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
49
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
50 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
51 8 gdevic
    if (M2 & T3) begin fMRead=1; nextM=1; end
52
    if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
53
    if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
54
    if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
55
    if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
56
    if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
57 6 gdevic
end
58
 
59 8 gdevic
if (~use_ixiy & pla[58]) begin
60
    if (M1 & T1) begin
61
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
62 6 gdevic
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
63
                    ctl_sw_2d=1;
64
                    ctl_sw_1d=1;
65
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
66 8 gdevic
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
67
    if (M2 & T1) begin fMRead=1;
68 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
69
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
70 8 gdevic
    if (M2 & T2) begin fMRead=1; end
71
    if (M2 & T3) begin fMRead=1; setM1=1; end
72
    if (M4 & T1) begin fMRead=1;
73 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
74 8 gdevic
    if (M4 & T2) begin fMRead=1; end
75
    if (M4 & T3) begin fMRead=1; setM1=1; end
76 6 gdevic
end
77
 
78 8 gdevic
if (use_ixiy & pla[59]) begin
79
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
80
    if (M2 & T1) begin fMRead=1;
81 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
82
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
83 8 gdevic
    if (M2 & T2) begin fMRead=1;
84
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
85
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
86 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
87 8 gdevic
    if (M2 & T3) begin fMRead=1; nextM=1; end
88
    if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
89
    if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
90
    if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
91
    if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
92
    if (M3 & T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end
93 6 gdevic
end
94
 
95 8 gdevic
if (~use_ixiy & pla[59]) begin
96
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mWrite=1;
97
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
98
                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
99 6 gdevic
                    ctl_sw_1u=1;
100
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
101 8 gdevic
    if (M2 & T1) begin fMWrite=1;
102 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
103
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
104 8 gdevic
    if (M2 & T2) begin fMWrite=1; end
105
    if (M2 & T3) begin fMWrite=1; setM1=1; end
106
    if (M4 & T1) begin fMWrite=1;
107 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
108 8 gdevic
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
109
                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
110 6 gdevic
                    ctl_sw_1u=1;
111
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
112 8 gdevic
    if (M4 & T2) begin fMWrite=1; end
113
    if (M4 & T3) begin fMWrite=1; setM1=1; end
114 6 gdevic
end
115
 
116
if (pla[40]) begin
117 8 gdevic
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
118
    if (M2 & T1) begin fMRead=1;
119 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
120
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
121 8 gdevic
    if (M2 & T2) begin fMRead=1;
122
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
123
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
124 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
125 8 gdevic
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1; end
126
    if (M3 & T1) begin fMRead=1;
127 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
128
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ ixy_d=1; /* Compute WZ=IX+d */ end
129 8 gdevic
    if (M3 & T2) begin fMRead=1;
130
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
131
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
132 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ ixy_d=1; /* Compute WZ=IX+d */ end
133 8 gdevic
    if (M3 & T3) begin fMRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
134
    if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
135
    if (M3 & T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end
136 6 gdevic
end
137
 
138 8 gdevic
if (pla[50] & ~pla[40]) begin
139
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
140
    if (M2 & T1) begin fMRead=1;
141 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
142
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
143 8 gdevic
    if (M2 & T2) begin fMRead=1;
144
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
145
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
146 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
147 8 gdevic
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1; end
148
    if (M3 & T1) begin fMWrite=1;
149 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
150
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
151 8 gdevic
    if (M3 & T2) begin fMWrite=1; end
152
    if (M3 & T3) begin fMWrite=1; setM1=1; end
153
    if (M4 & T1) begin fMWrite=1;
154 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
155 8 gdevic
    if (M4 & T2) begin fMWrite=1; end
156
    if (M4 & T3) begin fMWrite=1; setM1=1; end
157 6 gdevic
end
158
 
159 8 gdevic
if (pla[8] & pla[13]) begin
160
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mWrite=1;
161 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
162 8 gdevic
                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
163 6 gdevic
                    ctl_sw_2u=1;
164
                    ctl_sw_1u=1;
165
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
166 8 gdevic
    if (M2 & T1) begin fMWrite=1;
167 6 gdevic
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
168
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
169 8 gdevic
    if (M2 & T2) begin fMWrite=1;
170 6 gdevic
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
171 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
172 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
173 8 gdevic
    if (M2 & T3) begin fMWrite=1; setM1=1; end
174 6 gdevic
end
175
 
176 8 gdevic
if (pla[8] & ~pla[13]) begin
177
    if (M1 & T1) begin
178 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
179
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
180
                    ctl_sw_2d=1;
181
                    ctl_sw_1d=1;
182
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
183 8 gdevic
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
184
    if (M2 & T1) begin fMRead=1;
185 6 gdevic
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
186
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
187 8 gdevic
    if (M2 & T2) begin fMRead=1;
188 6 gdevic
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
189 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
190 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
191 8 gdevic
    if (M2 & T3) begin fMRead=1; setM1=1; end
192 6 gdevic
end
193
 
194 8 gdevic
if (pla[38] & pla[13]) begin
195
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
196
    if (M2 & T1) begin fMRead=1;
197 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
198
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
199 8 gdevic
    if (M2 & T2) begin fMRead=1;
200
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
201
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
202 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
203 8 gdevic
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
204
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
205 6 gdevic
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
206
                    ctl_sw_2d=1;
207
                    ctl_sw_1d=1;
208
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
209 8 gdevic
    if (M3 & T1) begin fMRead=1;
210 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
211
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
212 8 gdevic
    if (M3 & T2) begin fMRead=1;
213
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
214
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
215 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
216 8 gdevic
    if (M3 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
217 6 gdevic
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
218
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
219 8 gdevic
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
220 6 gdevic
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
221
                    ctl_sw_2d=1;
222
                    ctl_sw_1d=1;
223
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
224 8 gdevic
    if (M4 & T1) begin fMWrite=1;
225 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
226
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
227 8 gdevic
                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
228 6 gdevic
                    ctl_sw_2u=1;
229
                    ctl_sw_1u=1;
230
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
231 8 gdevic
    if (M4 & T2) begin fMWrite=1;
232 6 gdevic
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
233 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
234 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
235 8 gdevic
    if (M4 & T3) begin fMWrite=1; setM1=1; end
236 6 gdevic
end
237
 
238 8 gdevic
if (pla[38] & ~pla[13]) begin
239
    if (M1 & T1) begin
240 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
241
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
242
                    ctl_sw_2d=1;
243
                    ctl_sw_1d=1;
244
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
245 8 gdevic
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
246
    if (M2 & T1) begin fMRead=1;
247 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
248
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
249 8 gdevic
    if (M2 & T2) begin fMRead=1;
250
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
251
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
252 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
253 8 gdevic
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
254
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
255 6 gdevic
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
256
                    ctl_sw_2d=1;
257
                    ctl_sw_1d=1;
258
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
259 8 gdevic
    if (M3 & T1) begin fMRead=1;
260 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
261
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
262 8 gdevic
    if (M3 & T2) begin fMRead=1;
263
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
264
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
265 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
266 8 gdevic
    if (M3 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
267
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
268 6 gdevic
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
269
                    ctl_sw_2d=1;
270
                    ctl_sw_1d=1;
271
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
272 8 gdevic
    if (M4 & T1) begin fMRead=1;
273 6 gdevic
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
274
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
275 8 gdevic
    if (M4 & T2) begin fMRead=1;
276 6 gdevic
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
277 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
278 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
279 8 gdevic
    if (M4 & T3) begin fMRead=1; setM1=1; end
280 6 gdevic
end
281
 
282
if (pla[83]) begin
283 8 gdevic
    if (M1 & T1) begin
284 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
285
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
286
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
287
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
288
                    ctl_alu_res_oe=1; /* Result latch */
289
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
290
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
291
                    ctl_flags_sz_we=1;
292
                    ctl_flags_xy_we=1;
293
                    ctl_flags_hf_we=1;
294
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_IFF2;
295
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
296 8 gdevic
    if (M1 & T2) begin
297 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
298
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
299
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
300 8 gdevic
    if (M1 & T3) begin
301 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
302 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
303 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
304 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
305 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
306
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
307
                    ctl_flags_sz_we=1;
308
                    ctl_flags_xy_we=1;
309
                    ctl_flags_hf_we=1;
310
                    ctl_flags_pf_we=1;
311
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
312
                    ctl_flags_cf_we=1; end
313 8 gdevic
    if (M1 & T4) begin validPLA=1;
314
                    ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4u=1; /* Read either I or R based on op3 (0 or 1) */
315
                    ctl_reg_out_hi=~rsel3; ctl_reg_out_lo=rsel3; ctl_sw_2u=~rsel3; ctl_sw_2d=rsel3; /* Enable register gate based on the rsel3 */ /* Controlled by register gate */
316 6 gdevic
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
317 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
318 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
319
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
320
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
321
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
322
                    ctl_flags_sz_we=1;
323
                    ctl_flags_xy_we=1;
324
                    ctl_flags_hf_we=1;
325
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
326 8 gdevic
    if (M1 & T5) begin setM1=1; end
327 6 gdevic
end
328
 
329
if (pla[57]) begin
330 8 gdevic
    if (M1 & T3) begin
331 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
332 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
333 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
334 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
335 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
336
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
337
                    ctl_flags_sz_we=1;
338
                    ctl_flags_xy_we=1;
339
                    ctl_flags_hf_we=1;
340
                    ctl_flags_pf_we=1;
341
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
342
                    ctl_flags_cf_we=1; end
343 8 gdevic
    if (M1 & T4) begin validPLA=1;
344
                    ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4d=1; /* Write either I or R based on op3 (0 or 1) */
345 6 gdevic
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
346
                    ctl_sw_2u=1;
347
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
348
                    ctl_alu_op1_oe=1; /* OP1 latch */ end
349 8 gdevic
    if (M1 & T5) begin setM1=1; end
350 6 gdevic
end
351
 
352
// 16-bit Load Group
353
if (pla[7]) begin
354 8 gdevic
    if (M1 & T1) begin
355 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
356
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
357
                    ctl_sw_2d=1;
358
                    ctl_sw_1d=1;
359
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
360
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
361 8 gdevic
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
362
    if (M2 & T1) begin fMRead=1;
363 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
364
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
365 8 gdevic
    if (M2 & T2) begin fMRead=1;
366
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
367
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
368 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
369 8 gdevic
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1; end
370
    if (M3 & T1) begin fMRead=1;
371 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
372
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
373
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
374
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
375
                    ctl_sw_2d=1;
376
                    ctl_sw_1d=1;
377
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
378
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
379 8 gdevic
    if (M3 & T2) begin fMRead=1;
380
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
381
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
382 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
383 8 gdevic
    if (M3 & T3) begin fMRead=1; setM1=1; end
384 6 gdevic
end
385
 
386 8 gdevic
if (pla[30] & pla[13]) begin
387
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
388
    if (M2 & T1) begin fMRead=1;
389 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
390
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
391 8 gdevic
    if (M2 & T2) begin fMRead=1;
392
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
393
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
394 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
395 8 gdevic
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
396
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
397 6 gdevic
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
398
                    ctl_sw_2d=1;
399
                    ctl_sw_1d=1;
400
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
401 8 gdevic
    if (M3 & T1) begin fMRead=1;
402 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
403
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
404 8 gdevic
    if (M3 & T2) begin fMRead=1;
405
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
406
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
407 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
408 8 gdevic
    if (M3 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
409 6 gdevic
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
410
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
411 8 gdevic
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
412 6 gdevic
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
413
                    ctl_sw_2d=1;
414
                    ctl_sw_1d=1;
415
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
416 8 gdevic
    if (M4 & T1) begin fMWrite=1;
417 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
418
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
419 8 gdevic
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
420 6 gdevic
                    ctl_sw_1u=1;
421
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
422 8 gdevic
    if (M4 & T2) begin fMWrite=1;
423 6 gdevic
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
424 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
425 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
426 8 gdevic
    if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
427 6 gdevic
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
428
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
429 8 gdevic
    if (M5 & T1) begin fMWrite=1;
430 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
431
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
432 8 gdevic
                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
433 6 gdevic
                    ctl_sw_2u=1;
434
                    ctl_sw_1u=1;
435
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
436 8 gdevic
    if (M5 & T2) begin fMWrite=1;
437 6 gdevic
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
438 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
439 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
440 8 gdevic
    if (M5 & T3) begin fMWrite=1; setM1=1; end
441 6 gdevic
end
442
 
443 8 gdevic
if (pla[30] & ~pla[13]) begin
444
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
445
    if (M2 & T1) begin fMRead=1;
446 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
447
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
448 8 gdevic
    if (M2 & T2) begin fMRead=1;
449
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
450
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
451 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
452 8 gdevic
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
453
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
454 6 gdevic
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
455
                    ctl_sw_2d=1;
456
                    ctl_sw_1d=1;
457
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
458 8 gdevic
    if (M3 & T1) begin fMRead=1;
459 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
460
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
461 8 gdevic
    if (M3 & T2) begin fMRead=1;
462
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
463
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
464 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
465 8 gdevic
    if (M3 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
466
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
467 6 gdevic
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
468
                    ctl_sw_2d=1;
469
                    ctl_sw_1d=1;
470
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
471 8 gdevic
    if (M4 & T1) begin fMRead=1;
472 6 gdevic
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
473
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
474 8 gdevic
    if (M4 & T2) begin fMRead=1;
475 6 gdevic
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
476 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
477 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
478 8 gdevic
    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
479 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
480
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
481
                    ctl_sw_2d=1;
482
                    ctl_sw_1d=1;
483
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
484 8 gdevic
    if (M5 & T1) begin fMRead=1;
485 6 gdevic
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
486
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
487 8 gdevic
    if (M5 & T2) begin fMRead=1;
488 6 gdevic
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
489 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
490 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
491 8 gdevic
    if (M5 & T3) begin fMRead=1; setM1=1;
492 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
493
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
494
                    ctl_sw_2d=1;
495
                    ctl_sw_1d=1;
496
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
497
end
498
 
499 8 gdevic
if (pla[31] & pla[33]) begin
500
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
501
    if (M2 & T1) begin fMRead=1;
502 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
503
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
504 8 gdevic
    if (M2 & T2) begin fMRead=1;
505
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
506
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
507 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
508 8 gdevic
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
509
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
510 6 gdevic
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
511
                    ctl_sw_2d=1;
512
                    ctl_sw_1d=1;
513
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
514 8 gdevic
    if (M3 & T1) begin fMRead=1;
515 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
516
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
517 8 gdevic
    if (M3 & T2) begin fMRead=1;
518
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
519
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
520 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
521 8 gdevic
    if (M3 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
522 6 gdevic
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
523
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
524 8 gdevic
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
525 6 gdevic
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
526
                    ctl_sw_2d=1;
527
                    ctl_sw_1d=1;
528
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
529 8 gdevic
    if (M4 & T1) begin fMWrite=1;
530 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
531
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
532 8 gdevic
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
533 6 gdevic
                    ctl_sw_1u=1;
534
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
535
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
536 8 gdevic
    if (M4 & T2) begin fMWrite=1;
537 6 gdevic
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
538 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
539 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
540 8 gdevic
    if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
541 6 gdevic
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
542
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
543 8 gdevic
    if (M5 & T1) begin fMWrite=1;
544 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
545
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
546 8 gdevic
                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
547 6 gdevic
                    ctl_sw_2u=1;
548
                    ctl_sw_1u=1;
549
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
550
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
551 8 gdevic
    if (M5 & T2) begin fMWrite=1;
552 6 gdevic
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
553 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
554 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
555 8 gdevic
    if (M5 & T3) begin fMWrite=1; setM1=1; end
556 6 gdevic
end
557
 
558 8 gdevic
if (pla[31] & ~pla[33]) begin
559
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
560
    if (M2 & T1) begin fMRead=1;
561 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
562
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
563 8 gdevic
    if (M2 & T2) begin fMRead=1;
564
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
565
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
566 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
567 8 gdevic
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
568
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
569 6 gdevic
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
570
                    ctl_sw_2d=1;
571
                    ctl_sw_1d=1;
572
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
573 8 gdevic
    if (M3 & T1) begin fMRead=1;
574 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
575
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
576 8 gdevic
    if (M3 & T2) begin fMRead=1;
577
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
578
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
579 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
580 8 gdevic
    if (M3 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
581
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
582 6 gdevic
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
583
                    ctl_sw_2d=1;
584
                    ctl_sw_1d=1;
585
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
586 8 gdevic
    if (M4 & T1) begin fMRead=1;
587 6 gdevic
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
588
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
589 8 gdevic
    if (M4 & T2) begin fMRead=1;
590 6 gdevic
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
591 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
592 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
593 8 gdevic
    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
594 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
595
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
596
                    ctl_sw_2d=1;
597
                    ctl_sw_1d=1;
598
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
599
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
600 8 gdevic
    if (M5 & T1) begin fMRead=1;
601 6 gdevic
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
602
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
603 8 gdevic
    if (M5 & T2) begin fMRead=1;
604 6 gdevic
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
605 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
606 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
607 8 gdevic
    if (M5 & T3) begin fMRead=1; setM1=1;
608 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
609
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
610
                    ctl_sw_2d=1;
611
                    ctl_sw_1d=1;
612
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
613
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
614
end
615
 
616
if (pla[5]) begin
617 8 gdevic
    if (M1 & T4) begin validPLA=1;
618 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
619
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
620 8 gdevic
    if (M1 & T5) begin
621 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
622
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
623 8 gdevic
    if (M1 & T6) begin setM1=1; end
624 6 gdevic
end
625
 
626 8 gdevic
if (pla[23] & pla[16]) begin
627
    if (M1 & T4) begin validPLA=1; end
628
    if (M1 & T5) begin nextM=1; ctl_mWrite=1;
629 6 gdevic
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
630 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
631 6 gdevic
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
632 8 gdevic
    if (M2 & T1) begin fMWrite=1;
633
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
634 6 gdevic
                    ctl_apin_mux=1; /* Apin sourced from incrementer */
635
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
636 8 gdevic
                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
637 6 gdevic
                    ctl_sw_2u=1;
638
                    ctl_sw_1u=1;
639
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
640 8 gdevic
    if (M2 & T2) begin fMWrite=1;
641 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
642 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
643 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
644 8 gdevic
    if (M2 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
645 6 gdevic
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
646 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
647 6 gdevic
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
648 8 gdevic
    if (M3 & T1) begin fMWrite=1;
649
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
650 6 gdevic
                    ctl_apin_mux=1; /* Apin sourced from incrementer */
651
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
652 8 gdevic
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
653 6 gdevic
                    ctl_sw_1u=1;
654
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
655 8 gdevic
    if (M3 & T2) begin fMWrite=1;
656 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
657 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
658 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
659 8 gdevic
    if (M3 & T3) begin fMWrite=1; setM1=1; end
660 6 gdevic
end
661
 
662 8 gdevic
if (pla[23] & ~pla[16]) begin
663
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
664
    if (M2 & T1) begin fMRead=1;
665 6 gdevic
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
666
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
667 8 gdevic
    if (M2 & T2) begin fMRead=1;
668 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
669 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
670 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
671 8 gdevic
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
672 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
673
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
674
                    ctl_sw_2d=1;
675
                    ctl_sw_1d=1;
676
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
677 8 gdevic
    if (M3 & T1) begin fMRead=1;
678 6 gdevic
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
679
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
680 8 gdevic
    if (M3 & T2) begin fMRead=1;
681 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
682 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
683 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
684 8 gdevic
    if (M3 & T3) begin fMRead=1; setM1=1;
685 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
686
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
687
                    ctl_sw_2d=1;
688
                    ctl_sw_1d=1;
689
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
690
end
691
 
692
// Exchange, Block Transfer and Search Groups
693
if (pla[2]) begin
694 8 gdevic
    if (M1 & T2) begin
695 6 gdevic
                    ctl_reg_ex_de_hl=1; /* EX DE,HL */ end
696 8 gdevic
    if (M1 & T4) begin validPLA=1; setM1=1; end
697 6 gdevic
end
698
 
699
if (pla[39]) begin
700 8 gdevic
    if (M1 & T2) begin
701 6 gdevic
                    ctl_reg_ex_af=1; /* EX AF,AF' */ end
702 8 gdevic
    if (M1 & T4) begin validPLA=1; setM1=1; end
703 6 gdevic
end
704
 
705
if (pla[1]) begin
706 8 gdevic
    if (M1 & T2) begin
707 6 gdevic
                    ctl_reg_exx=1; /* EXX */ end
708 8 gdevic
    if (M1 & T4) begin validPLA=1; setM1=1; end
709 6 gdevic
end
710
 
711
if (pla[10]) begin
712 8 gdevic
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
713
    if (M2 & T1) begin fMRead=1;
714 6 gdevic
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
715
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
716 8 gdevic
    if (M2 & T2) begin fMRead=1;
717 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
718 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
719 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
720 8 gdevic
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
721
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
722 6 gdevic
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
723
                    ctl_sw_2d=1;
724
                    ctl_sw_1d=1;
725
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
726 8 gdevic
    if (M3 & T1) begin fMRead=1;
727 6 gdevic
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
728
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
729 8 gdevic
    if (M3 & T2) begin fMRead=1;
730 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
731 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
732 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
733 8 gdevic
    if (M3 & T3) begin fMRead=1;
734
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
735 6 gdevic
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
736
                    ctl_sw_2d=1;
737
                    ctl_sw_1d=1;
738
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
739 8 gdevic
    if (M3 & T4) begin nextM=1; ctl_mWrite=1;
740 6 gdevic
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
741 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
742 6 gdevic
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
743 8 gdevic
    if (M4 & T1) begin fMWrite=1;
744
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
745 6 gdevic
                    ctl_apin_mux=1; /* Apin sourced from incrementer */
746
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
747 8 gdevic
                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
748 6 gdevic
                    ctl_sw_2u=1;
749
                    ctl_sw_1u=1;
750
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
751 8 gdevic
    if (M4 & T2) begin fMWrite=1;
752 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
753 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
754 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
755 8 gdevic
    if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
756 6 gdevic
                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
757 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
758 6 gdevic
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
759 8 gdevic
    if (M5 & T1) begin fMWrite=1;
760
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
761 6 gdevic
                    ctl_apin_mux=1; /* Apin sourced from incrementer */
762
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
763 8 gdevic
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
764 6 gdevic
                    ctl_sw_1u=1;
765
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
766 8 gdevic
    if (M5 & T2) begin fMWrite=1;
767 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
768 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
769 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
770 8 gdevic
    if (M5 & T3) begin fMWrite=1;
771 6 gdevic
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
772
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
773 8 gdevic
    if (M5 & T4) begin
774 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
775
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
776 8 gdevic
    if (M5 & T5) begin setM1=1; end
777 6 gdevic
end
778
 
779
if (pla[0]) begin
780 8 gdevic
    begin nonRep=1; /* Non-repeating block instruction */ end
781 6 gdevic
end
782
 
783
if (pla[12]) begin
784 8 gdevic
    if (M1 & T1) begin
785 6 gdevic
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
786
                    ctl_alu_res_oe=1; /* Result latch */
787
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
788
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
789
                    ctl_flags_xy_we=1;
790
                    ctl_flags_hf_we=1;
791
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP;
792
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
793
                    ctl_flags_use_cf2=1; end
794 8 gdevic
    if (M1 & T2) begin
795 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
796
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
797
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
798 8 gdevic
    if (M1 & T3) begin
799 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
800 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
801 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
802 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
803 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
804
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
805
                    ctl_flags_sz_we=1;
806
                    ctl_flags_xy_we=1;
807
                    ctl_flags_hf_we=1;
808
                    ctl_flags_pf_we=1;
809
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
810
                    ctl_flags_cf_we=1; end
811 8 gdevic
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
812
    if (M2 & T1) begin fMRead=1;
813 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
814
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
815 8 gdevic
    if (M2 & T2) begin fMRead=1;
816 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
817 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
818 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
819 8 gdevic
    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
820 6 gdevic
                    ctl_sw_2d=1;
821
                    ctl_sw_1d=1;
822
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
823
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
824 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
825 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
826
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
827 8 gdevic
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
828 6 gdevic
                    ctl_flags_hf_we=1;
829 8 gdevic
                    ctl_flags_cf2_we=1; end
830
    if (M3 & T1) begin fMWrite=1;
831 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit DE, enable SW4 downstream */
832
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
833
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
834
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
835
                    ctl_alu_res_oe=1; /* Result latch */
836
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
837 8 gdevic
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
838 6 gdevic
                    ctl_flags_use_cf2=1; end
839 8 gdevic
    if (M3 & T2) begin fMWrite=1;
840 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
841 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
842 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
843 8 gdevic
    if (M3 & T3) begin fMWrite=1;
844 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
845
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
846 8 gdevic
    if (M3 & T4) begin
847 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
848 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
849 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
850
                    ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end
851 8 gdevic
    if (M3 & T5) begin nextM=1; setM1=nonRep | ~repeat_en; end
852
    if (M4 & T1) begin
853 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
854
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
855 8 gdevic
    if (M4 & T2) begin
856
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
857
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
858 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
859 8 gdevic
    if (M4 & T3) begin
860 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
861
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
862 8 gdevic
    if (M4 & T4) begin
863
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
864
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
865 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
866 8 gdevic
    if (M4 & T5) begin setM1=1; end
867 6 gdevic
end
868
 
869
if (pla[11]) begin
870 8 gdevic
    if (M1 & T1) begin
871 6 gdevic
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
872
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
873
                    ctl_alu_res_oe=1; /* Result latch */
874
                    ctl_alu_op1_sel_zero=1; /* Zero */
875
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
876 8 gdevic
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
877 6 gdevic
                    ctl_flags_xy_we=1;
878
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP;
879
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
880
                    ctl_flags_use_cf2=1; end
881 8 gdevic
    if (M1 & T2) begin
882 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
883
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
884
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
885
                    ctl_flags_hf_cpl=flags_nf; end
886 8 gdevic
    if (M1 & T3) begin
887 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
888 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
889 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
890 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
891 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
892
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
893
                    ctl_flags_sz_we=1;
894
                    ctl_flags_xy_we=1;
895
                    ctl_flags_hf_we=1;
896
                    ctl_flags_pf_we=1;
897
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
898
                    ctl_flags_cf_we=1; end
899 8 gdevic
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
900
    if (M2 & T1) begin fMRead=1;
901 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
902
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
903 8 gdevic
    if (M2 & T2) begin fMRead=1;
904 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
905 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
906 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
907 8 gdevic
    if (M2 & T3) begin fMRead=1; nextM=1;
908 6 gdevic
                    ctl_sw_2d=1;
909
                    ctl_sw_1d=1;
910
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
911
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
912 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
913 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
914
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
915 8 gdevic
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
916 6 gdevic
                    ctl_flags_hf_we=1;
917 8 gdevic
                    ctl_flags_cf2_we=1; end
918
    if (M3 & T1) begin
919 6 gdevic
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
920
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
921
                    ctl_alu_res_oe=1; /* Result latch */
922
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
923 8 gdevic
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
924 6 gdevic
                    ctl_flags_sz_we=1;
925
                    ctl_flags_use_cf2=1; end
926 8 gdevic
    if (M3 & T3) begin
927 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
928
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
929 8 gdevic
    if (M3 & T4) begin
930 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
931 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
932 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
933
                    ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end
934 8 gdevic
    if (M3 & T5) begin nextM=1; setM1=nonRep | ~repeat_en | flags_zf; end
935
    if (M4 & T1) begin
936 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
937
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
938 8 gdevic
    if (M4 & T2) begin
939
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
940
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
941 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
942 8 gdevic
    if (M4 & T3) begin
943 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
944
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
945 8 gdevic
    if (M4 & T4) begin
946
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
947
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
948 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
949 8 gdevic
    if (M4 & T5) begin setM1=1; end
950 6 gdevic
end
951
 
952
// 8-bit Arithmetic and Logic Group
953 8 gdevic
if (pla[65] & ~pla[52]) begin
954
    if (M1 & T1) begin /* Which register to be written is decided elsewhere */
955 6 gdevic
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
956
                    ctl_sw_2u=1;
957
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
958
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
959
                    ctl_alu_res_oe=1; /* Result latch */
960
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
961
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
962
                    ctl_flags_sz_we=1;
963
                    ctl_flags_cf_we=1; end
964 8 gdevic
    if (M1 & T2) begin
965 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
966
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
967
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
968
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
969
                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
970 8 gdevic
    if (M1 & T3) begin
971 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
972 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
973 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
974 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
975 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
976
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
977
                    ctl_flags_sz_we=1;
978
                    ctl_flags_xy_we=1;
979
                    ctl_flags_hf_we=1;
980
                    ctl_flags_pf_we=1;
981
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
982
                    ctl_flags_cf_we=1; end
983 8 gdevic
    if (M1 & T4) begin validPLA=1; setM1=1;
984
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
985
                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
986 6 gdevic
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
987 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
988 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
989
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
990
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
991
                    ctl_flags_sz_we=1;
992
                    ctl_flags_xy_we=1;
993
                    ctl_flags_hf_we=1; end
994
end
995
 
996
if (pla[64]) begin
997 8 gdevic
    if (M1 & T1) begin /* Which register to be written is decided elsewhere */
998 6 gdevic
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
999
                    ctl_sw_2u=1;
1000
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1001
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1002
                    ctl_alu_res_oe=1; /* Result latch */
1003
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1004
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1005
                    ctl_flags_sz_we=1;
1006
                    ctl_flags_cf_we=1; end
1007 8 gdevic
    if (M1 & T2) begin
1008 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1009
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1010
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1011
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1012
                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
1013 8 gdevic
    if (M1 & T3) begin
1014 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1015 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1016 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1017 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1018 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1019
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1020
                    ctl_flags_sz_we=1;
1021
                    ctl_flags_xy_we=1;
1022
                    ctl_flags_hf_we=1;
1023
                    ctl_flags_pf_we=1;
1024
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1025
                    ctl_flags_cf_we=1; end
1026 8 gdevic
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1;
1027
                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
1028
                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
1029 6 gdevic
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1030 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1031 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1032
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1033
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1034
                    ctl_flags_sz_we=1;
1035
                    ctl_flags_xy_we=1;
1036
                    ctl_flags_hf_we=1; end
1037 8 gdevic
    if (M2 & T1) begin fMRead=1;
1038 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
1039
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
1040
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ end
1041 8 gdevic
    if (M2 & T2) begin fMRead=1;
1042
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
1043
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
1044 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1045 8 gdevic
    if (M2 & T3) begin fMRead=1; setM1=1;
1046 6 gdevic
                    ctl_sw_2d=1;
1047
                    ctl_sw_1d=1;
1048
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1049
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1050 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1051 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1052
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1053
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1054
                    ctl_flags_sz_we=1;
1055
                    ctl_flags_xy_we=1;
1056
                    ctl_flags_hf_we=1; end
1057
end
1058
 
1059 8 gdevic
if (use_ixiy & pla[52]) begin
1060
    if (M1 & T3) begin
1061 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1062 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1063 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1064 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1065 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1066
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1067
                    ctl_flags_sz_we=1;
1068
                    ctl_flags_xy_we=1;
1069
                    ctl_flags_hf_we=1;
1070
                    ctl_flags_pf_we=1;
1071
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1072
                    ctl_flags_cf_we=1; end
1073 8 gdevic
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
1074
    if (M2 & T1) begin fMRead=1;
1075 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
1076
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
1077 8 gdevic
    if (M2 & T2) begin fMRead=1;
1078
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
1079
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
1080 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1081 8 gdevic
    if (M2 & T3) begin fMRead=1; nextM=1; end
1082
    if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
1083
    if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
1084
    if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
1085
    if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
1086
    if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
1087 6 gdevic
end
1088
 
1089 8 gdevic
if (~use_ixiy & pla[52]) begin
1090
    if (M1 & T1) begin /* Which register to be written is decided elsewhere */
1091 6 gdevic
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1092
                    ctl_sw_2u=1;
1093
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1094
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1095
                    ctl_alu_res_oe=1; /* Result latch */
1096
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1097
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1098
                    ctl_flags_sz_we=1;
1099
                    ctl_flags_cf_we=1; end
1100 8 gdevic
    if (M1 & T2) begin
1101 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1102
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1103
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1104
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1105
                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
1106 8 gdevic
    if (M1 & T3) begin
1107 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1108 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1109 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1110 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1111 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1112
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1113
                    ctl_flags_sz_we=1;
1114
                    ctl_flags_xy_we=1;
1115
                    ctl_flags_hf_we=1;
1116
                    ctl_flags_pf_we=1;
1117
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1118
                    ctl_flags_cf_we=1; end
1119 8 gdevic
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
1120
    if (M2 & T1) begin fMRead=1;
1121 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
1122
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
1123 8 gdevic
    if (M2 & T2) begin fMRead=1;
1124 6 gdevic
                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
1125 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
1126 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1127 8 gdevic
    if (M2 & T3) begin fMRead=1; setM1=1;
1128 6 gdevic
                    ctl_sw_2d=1;
1129
                    ctl_sw_1d=1;
1130
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1131
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1132 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1133 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1134
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1135
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1136
                    ctl_flags_sz_we=1;
1137
                    ctl_flags_xy_we=1;
1138
                    ctl_flags_hf_we=1; end
1139 8 gdevic
    if (M4 & T1) begin fMRead=1;
1140 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1141 8 gdevic
    if (M4 & T2) begin fMRead=1;
1142 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1143 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1144 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1145 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1146 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1147
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1148
                    ctl_flags_sz_we=1;
1149
                    ctl_flags_xy_we=1;
1150
                    ctl_flags_hf_we=1;
1151
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1152
                    ctl_flags_cf_we=1; end
1153 8 gdevic
    if (M4 & T3) begin fMRead=1; setM1=1;
1154 6 gdevic
                    ctl_sw_2d=1;
1155
                    ctl_sw_1d=1;
1156
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1157
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1158 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1159 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1160
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1161
                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
1162
                    ctl_flags_sz_we=1;
1163
                    ctl_flags_xy_we=1;
1164
                    ctl_flags_hf_we=1; end
1165
end
1166
 
1167 8 gdevic
if (pla[66] & ~pla[53]) begin
1168
    if (M1 & T1) begin
1169
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
1170 6 gdevic
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1171
                    ctl_sw_2u=1;
1172
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1173
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1174
                    ctl_alu_res_oe=1; /* Result latch */
1175
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1176 8 gdevic
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1177 6 gdevic
                    ctl_flags_sz_we=1;
1178
                    ctl_flags_xy_we=1;
1179
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
1180
                    ctl_flags_use_cf2=1; end
1181 8 gdevic
    if (M1 & T2) begin
1182 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1183
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1184
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1185
                    ctl_flags_hf_cpl=flags_nf; end
1186 8 gdevic
    if (M1 & T3) begin
1187 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1188 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1189 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1190 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1191 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1192
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1193
                    ctl_flags_sz_we=1;
1194
                    ctl_flags_xy_we=1;
1195
                    ctl_flags_hf_we=1;
1196
                    ctl_flags_pf_we=1;
1197
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1198
                    ctl_flags_cf_we=1; end
1199 8 gdevic
    if (M1 & T4) begin validPLA=1; setM1=1;
1200
        if (op4 & op5 & ~op3) begin ctl_bus_zero_oe=1; end  /* Trying to read flags? Put 0 on the bus instead. */
1201
        if (~(op4 & op5 & ~op3)) begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; end /* Read 8-bit GP register */
1202
                    ctl_reg_out_hi=~rsel3; ctl_reg_out_lo=rsel3; ctl_sw_2u=~rsel3; ctl_sw_2d=rsel3; /* Enable register gate based on the rsel3 */ /* Controlled by register gate */
1203 6 gdevic
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1204 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1205 6 gdevic
                    ctl_alu_op2_sel_zero=1; /* Zero */
1206
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1207
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1208 8 gdevic
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1209 6 gdevic
                    ctl_flags_sz_we=1;
1210
                    ctl_flags_xy_we=1;
1211
                    ctl_flags_hf_we=1;
1212
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1213
                    ctl_flags_cf_set=1; /* Set CF going into the ALU core */
1214 8 gdevic
                    ctl_flags_cf2_we=1; end
1215 6 gdevic
end
1216
 
1217
if (pla[75]) begin
1218 8 gdevic
    if (M1 & T1) begin
1219 6 gdevic
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1220
                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */
1221
                    ctl_alu_sel_op2_neg=1; end
1222 8 gdevic
    if (M1 & T4) begin
1223 6 gdevic
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1224
                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */
1225
                    ctl_alu_sel_op2_neg=1; end
1226
end
1227
 
1228 8 gdevic
if ((M2 | M4) & pla[75]) begin
1229
    begin
1230 6 gdevic
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1231
                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */
1232
                    ctl_alu_sel_op2_neg=1; end
1233
end
1234
 
1235 8 gdevic
if (use_ixiy & pla[53]) begin
1236
    if (M1 & T3) begin
1237 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1238 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1239 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1240 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1241 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1242
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1243
                    ctl_flags_sz_we=1;
1244
                    ctl_flags_xy_we=1;
1245
                    ctl_flags_hf_we=1;
1246
                    ctl_flags_pf_we=1;
1247
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1248
                    ctl_flags_cf_we=1; end
1249 8 gdevic
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
1250
    if (M2 & T1) begin fMRead=1;
1251 6 gdevic
                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
1252
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
1253 8 gdevic
    if (M2 & T2) begin fMRead=1;
1254
                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
1255
                    ctl_inc_cy=~pc_inc_hold; /* Increment */
1256 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1257 8 gdevic
    if (M2 & T3) begin fMRead=1; nextM=1; end
1258
    if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
1259
    if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
1260
    if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
1261
    if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
1262
    if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
1263 6 gdevic
end
1264
 
1265 8 gdevic
if (~use_ixiy & pla[53]) begin
1266
    if (M1 & T2) begin
1267 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1268
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1269
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1270
                    ctl_flags_hf_cpl=flags_nf; end
1271 8 gdevic
    if (M1 & T3) begin
1272 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1273 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1274 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1275 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1276 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1277
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1278
                    ctl_flags_sz_we=1;
1279
                    ctl_flags_xy_we=1;
1280
                    ctl_flags_hf_we=1;
1281
                    ctl_flags_pf_we=1;
1282
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1283
                    ctl_flags_cf_we=1; end
1284 8 gdevic
    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
1285
    if (M2 & T1) begin fMRead=1;
1286 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
1287
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
1288 8 gdevic
    if (M2 & T2) begin fMRead=1; end
1289
    if (M2 & T3) begin fMRead=1;
1290 6 gdevic
                    ctl_sw_2d=1;
1291
                    ctl_sw_1d=1;
1292
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1293
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1294 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1295 6 gdevic
                    ctl_alu_op2_sel_zero=1; /* Zero */
1296
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1297
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1298 8 gdevic
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1299 6 gdevic
                    ctl_flags_hf_we=1;
1300
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1301
                    ctl_flags_cf_set=1; /* Set CF going into the ALU core */
1302 8 gdevic
                    ctl_flags_cf2_we=1; end
1303
    if (M2 & T4) begin nextM=1; ctl_mWrite=1;
1304 6 gdevic
                    ctl_sw_2u=1;
1305
                    ctl_sw_1u=1;
1306
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
1307
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1308
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1309
                    ctl_alu_res_oe=1; /* Result latch */
1310
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1311 8 gdevic
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1312 6 gdevic
                    ctl_flags_sz_we=1;
1313
                    ctl_flags_xy_we=1;
1314
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
1315
                    ctl_flags_use_cf2=1; end
1316 8 gdevic
    if (M3 & T1) begin fMWrite=1;
1317 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1318 8 gdevic
    if (M3 & T2) begin fMWrite=1; end
1319
    if (M3 & T3) begin fMWrite=1; setM1=1; end
1320
    if (M4 & T1) begin fMRead=1;
1321 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1322 8 gdevic
    if (M4 & T2) begin fMRead=1; end
1323
    if (M4 & T3) begin fMRead=1;
1324 6 gdevic
                    ctl_sw_2d=1;
1325
                    ctl_sw_1d=1;
1326
                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
1327
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1328 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1329 6 gdevic
                    ctl_alu_op2_sel_zero=1; /* Zero */
1330
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1331
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1332 8 gdevic
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1333 6 gdevic
                    ctl_flags_hf_we=1;
1334
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1335
                    ctl_flags_cf_set=1; /* Set CF going into the ALU core */
1336 8 gdevic
                    ctl_flags_cf2_we=1; end
1337
    if (M4 & T4) begin nextM=1; ctl_mWrite=1;
1338 6 gdevic
                    ctl_sw_2u=1;
1339
                    ctl_sw_1u=1;
1340
                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
1341
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1342
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1343
                    ctl_alu_res_oe=1; /* Result latch */
1344
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1345 8 gdevic
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1346 6 gdevic
                    ctl_flags_sz_we=1;
1347
                    ctl_flags_xy_we=1;
1348
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
1349
                    ctl_flags_use_cf2=1; end
1350 8 gdevic
    if (M5 & T1) begin fMWrite=1;
1351 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1352 8 gdevic
    if (M5 & T2) begin fMWrite=1; end
1353
    if (M5 & T3) begin fMWrite=1; setM1=1; end
1354 6 gdevic
end
1355
 
1356
// 16-bit Arithmetic Group
1357
if (pla[69]) begin
1358 8 gdevic
    if (M1 & T2) begin
1359 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1360
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1361
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
1362 8 gdevic
    if (M1 & T3) begin
1363 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1364 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1365 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1366 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1367 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1368
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1369
                    ctl_flags_sz_we=1;
1370
                    ctl_flags_xy_we=1;
1371
                    ctl_flags_hf_we=1;
1372
                    ctl_flags_pf_we=1;
1373
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1374
                    ctl_flags_cf_we=1; end
1375 8 gdevic
    if (M1 & T4) begin validPLA=1; nextM=1;
1376 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
1377 8 gdevic
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
1378 6 gdevic
                    ctl_sw_2d=1;
1379 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1380 6 gdevic
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
1381 8 gdevic
    if (M2 & T1) begin
1382 6 gdevic
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
1383 8 gdevic
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
1384 6 gdevic
                    ctl_sw_2d=1;
1385
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1386 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1387 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1388
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1389 8 gdevic
                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
1390 6 gdevic
                    ctl_flags_hf_we=1;
1391
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1392 8 gdevic
    if (M2 & T2) begin
1393
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
1394 6 gdevic
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
1395
                    ctl_sw_2u=1;
1396
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1397
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1398
                    ctl_alu_res_oe=1; /* Result latch */
1399
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1400 8 gdevic
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1401 6 gdevic
                    ctl_flags_xy_we=1;
1402
                    ctl_flags_cf_we=1; end
1403 8 gdevic
    if (M2 & T3) begin
1404 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
1405 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1406
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1407 6 gdevic
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
1408 8 gdevic
    if (M2 & T4) begin nextM=1;
1409 6 gdevic
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
1410 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1411 6 gdevic
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1412 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1413 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1414
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1415 8 gdevic
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1416 6 gdevic
                    ctl_flags_hf_we=1;
1417
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1418 8 gdevic
    if (M3 & T1) begin
1419 6 gdevic
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
1420
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
1421 8 gdevic
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
1422 6 gdevic
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
1423
                    ctl_sw_2u=1;
1424
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1425
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1426
                    ctl_alu_res_oe=1; /* Result latch */
1427
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1428 8 gdevic
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1429 6 gdevic
                    ctl_flags_xy_we=1;
1430
                    ctl_flags_cf_we=1; end
1431 8 gdevic
    if (M3 & T2) begin
1432 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
1433
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1434 8 gdevic
    if (M3 & T3) begin setM1=1; end
1435 6 gdevic
end
1436
 
1437 8 gdevic
if (op3 & pla[68]) begin
1438
    if (M1 & T2) begin
1439 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1440
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1441
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
1442 8 gdevic
    if (M1 & T3) begin
1443 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1444 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1445 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1446 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1447 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1448
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1449
                    ctl_flags_sz_we=1;
1450
                    ctl_flags_xy_we=1;
1451
                    ctl_flags_hf_we=1;
1452
                    ctl_flags_pf_we=1;
1453
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
1454
                    ctl_flags_cf_we=1; end
1455 8 gdevic
    if (M1 & T4) begin validPLA=1; nextM=1;
1456 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
1457 8 gdevic
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
1458 6 gdevic
                    ctl_sw_2d=1;
1459 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1460 6 gdevic
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
1461 8 gdevic
    if (M2 & T1) begin
1462 6 gdevic
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
1463 8 gdevic
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
1464 6 gdevic
                    ctl_sw_2d=1;
1465
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1466 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1467 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1468
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1469 8 gdevic
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1470 6 gdevic
                    ctl_flags_hf_we=1;
1471
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1472 8 gdevic
    if (M2 & T2) begin
1473
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
1474 6 gdevic
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
1475
                    ctl_sw_2u=1;
1476
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1477
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1478
                    ctl_alu_res_oe=1; /* Result latch */
1479
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1480 8 gdevic
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1481 6 gdevic
                    ctl_flags_sz_we=1;
1482
                    ctl_flags_xy_we=1;
1483
                    ctl_flags_cf_we=1; end
1484 8 gdevic
    if (M2 & T3) begin
1485 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
1486 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1487
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1488 6 gdevic
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
1489 8 gdevic
    if (M2 & T4) begin nextM=1;
1490 6 gdevic
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
1491 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1492 6 gdevic
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1493 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1494 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1495
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1496 8 gdevic
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1497 6 gdevic
                    ctl_flags_hf_we=1;
1498
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1499 8 gdevic
    if (M3 & T1) begin
1500 6 gdevic
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
1501
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
1502 8 gdevic
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
1503 6 gdevic
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
1504
                    ctl_sw_2u=1;
1505
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1506
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1507
                    ctl_alu_res_oe=1; /* Result latch */
1508
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1509 8 gdevic
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1510 6 gdevic
                    ctl_flags_sz_we=1;
1511
                    ctl_flags_xy_we=1;
1512
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
1513
                    ctl_flags_cf_we=1;
1514
                    ctl_alu_zero_16bit=1; /* 16-bit arithmetic operation uses ZF calculated over 2 bytes */ end
1515 8 gdevic
    if (M3 & T2) begin
1516 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
1517
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1518 8 gdevic
    if (M3 & T3) begin setM1=1; end
1519 6 gdevic
end
1520
 
1521 8 gdevic
if (~op3 & pla[68]) begin
1522
    if (M1 & T2) begin
1523 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1524
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1525
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1526
                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
1527 8 gdevic
    if (M1 & T3) begin
1528 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1529 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1530 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1531 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1532 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1533
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1534
                    ctl_flags_sz_we=1;
1535
                    ctl_flags_xy_we=1;
1536
                    ctl_flags_hf_we=1;
1537
                    ctl_flags_pf_we=1;
1538
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1539
                    ctl_flags_cf_we=1; end
1540 8 gdevic
    if (M1 & T4) begin validPLA=1; nextM=1;
1541 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
1542 8 gdevic
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
1543 6 gdevic
                    ctl_sw_2d=1;
1544 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1545 6 gdevic
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
1546 8 gdevic
    if (M2 & T1) begin
1547 6 gdevic
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
1548 8 gdevic
                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
1549 6 gdevic
                    ctl_sw_2d=1;
1550
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1551 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1552 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1553
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1554 8 gdevic
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
1555 6 gdevic
                    ctl_flags_hf_we=1;
1556
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1557 8 gdevic
    if (M2 & T2) begin
1558
                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
1559 6 gdevic
                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
1560
                    ctl_sw_2u=1;
1561
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1562
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1563
                    ctl_alu_res_oe=1; /* Result latch */
1564
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1565 8 gdevic
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
1566 6 gdevic
                    ctl_flags_sz_we=1;
1567
                    ctl_flags_xy_we=1;
1568
                    ctl_flags_cf_we=1; end
1569 8 gdevic
    if (M2 & T3) begin
1570 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
1571 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1572
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1573 6 gdevic
                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end
1574 8 gdevic
    if (M2 & T4) begin nextM=1;
1575 6 gdevic
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
1576 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1577 6 gdevic
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1578 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1579 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1580
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1581 8 gdevic
                    ctl_alu_sel_op2_neg=1; ctl_alu_core_hf|=~ctl_alu_op_low;
1582 6 gdevic
                    ctl_flags_hf_we=1;
1583
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1584 8 gdevic
    if (M3 & T1) begin
1585 6 gdevic
                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
1586
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
1587 8 gdevic
                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
1588 6 gdevic
                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
1589
                    ctl_sw_2u=1;
1590
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1591
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1592
                    ctl_alu_res_oe=1; /* Result latch */
1593
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1594 8 gdevic
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
1595 6 gdevic
                    ctl_flags_sz_we=1;
1596
                    ctl_flags_xy_we=1;
1597
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
1598
                    ctl_flags_cf_we=1;
1599
                    ctl_alu_zero_16bit=1; /* 16-bit arithmetic operation uses ZF calculated over 2 bytes */ end
1600 8 gdevic
    if (M3 & T2) begin
1601 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
1602
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
1603 8 gdevic
    if (M3 & T3) begin setM1=1; end
1604 6 gdevic
end
1605
 
1606
if (pla[9]) begin
1607 8 gdevic
    if (M1 & T4) begin validPLA=1;
1608 6 gdevic
                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
1609
                    ctl_al_we=1; /* Write a value from the register bus to the address latch */
1610
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1611 8 gdevic
    if (M1 & T5) begin
1612 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit general purpose register, enable SW4 upstream */
1613 8 gdevic
                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
1614 6 gdevic
                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
1615
                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
1616 8 gdevic
    if (M1 & T6) begin setM1=1; end
1617 6 gdevic
end
1618
 
1619
// General Purpose Arithmetic and CPU Control Groups
1620
if (pla[77]) begin
1621 8 gdevic
    if (M1 & T1) begin
1622 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
1623
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1624
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1625
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1626
                    ctl_alu_res_oe=1; /* Result latch */
1627
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1628 8 gdevic
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1629 6 gdevic
                    ctl_flags_sz_we=1;
1630
                    ctl_flags_xy_we=1;
1631
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
1632
                    ctl_flags_cf_we=1;
1633 8 gdevic
                    ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=~flags_nf; end
1634
    if (M1 & T2) begin
1635 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1636
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1637
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1638
                    ctl_flags_use_cf2=1;
1639
                    ctl_flags_hf_cpl=flags_nf; end
1640 8 gdevic
    if (M1 & T3) begin
1641 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1642 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1643 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1644 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1645 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1646
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1647
                    ctl_flags_sz_we=1;
1648
                    ctl_flags_xy_we=1;
1649
                    ctl_flags_hf2_we=1; /* Write HF2 flag (DAA only) */
1650
                    ctl_flags_pf_we=1;
1651
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1652
                    ctl_flags_cf_we=1; end
1653 8 gdevic
    if (M1 & T4) begin validPLA=1; setM1=1;
1654 6 gdevic
                    ctl_sw_2d=1;
1655
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1656 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1657 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1658
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1659 8 gdevic
                    ctl_alu_core_hf|=~ctl_alu_op_low;
1660 6 gdevic
                    ctl_flags_sz_we=1;
1661
                    ctl_flags_xy_we=1;
1662
                    ctl_flags_hf_we=1;
1663 8 gdevic
                    ctl_flags_cf_set=1; /* Set CF going into the ALU core */
1664
                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel_daa=1;
1665 6 gdevic
                    ctl_daa_oe=1; /* Write DAA correction factor to the bus */
1666 8 gdevic
                    ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=~flags_nf; end
1667 6 gdevic
end
1668
 
1669
if (pla[81]) begin
1670 8 gdevic
    if (M1 & T1) begin
1671 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
1672
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1673
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1674
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1675
                    ctl_alu_res_oe=1; /* Result latch */
1676
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1677
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1678
                    ctl_flags_xy_we=1;
1679
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1680
                    ctl_alu_sel_op2_neg=1; end
1681 8 gdevic
    if (M1 & T2) begin
1682 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1683
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1684
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1685
                    ctl_flags_hf_cpl=flags_nf; end
1686 8 gdevic
    if (M1 & T3) begin
1687 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1688 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1689 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1690 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1691 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1692
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1693
                    ctl_flags_sz_we=1;
1694
                    ctl_flags_xy_we=1;
1695
                    ctl_flags_hf_we=1;
1696
                    ctl_flags_pf_we=1;
1697
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1698
                    ctl_flags_cf_we=1; end
1699 8 gdevic
    if (M1 & T4) begin validPLA=1; setM1=1;
1700 6 gdevic
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1701
                    ctl_alu_op1_sel_zero=1; /* Zero */
1702
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1703
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1704
                    ctl_flags_xy_we=1;
1705
                    ctl_flags_hf_we=1;
1706
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1707
                    ctl_alu_sel_op2_neg=1; end
1708
end
1709
 
1710
if (pla[82]) begin
1711 8 gdevic
    if (M1 & T1) begin
1712 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
1713
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1714
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1715
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1716
                    ctl_alu_res_oe=1; /* Result latch */
1717
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1718 8 gdevic
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
1719 6 gdevic
                    ctl_flags_sz_we=1;
1720
                    ctl_flags_xy_we=1;
1721
                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
1722
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1723
                    ctl_flags_cf_we=1; end
1724 8 gdevic
    if (M1 & T2) begin
1725 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1726
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1727
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1728
                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
1729 8 gdevic
    if (M1 & T3) begin
1730 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1731 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1732 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1733 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1734 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1735
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1736
                    ctl_flags_sz_we=1;
1737
                    ctl_flags_xy_we=1;
1738
                    ctl_flags_hf_we=1;
1739
                    ctl_flags_pf_we=1;
1740
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1741
                    ctl_flags_cf_we=1; end
1742 8 gdevic
    if (M1 & T4) begin validPLA=1; setM1=1;
1743 6 gdevic
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1744
                    ctl_alu_op1_sel_zero=1; /* Zero */
1745
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1746 8 gdevic
                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
1747 6 gdevic
                    ctl_flags_sz_we=1;
1748
                    ctl_flags_xy_we=1;
1749
                    ctl_flags_hf_we=1;
1750
                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;
1751
                    ctl_flags_cf_we=1; end
1752
end
1753
 
1754
if (pla[89]) begin
1755 8 gdevic
    if (M1 & T1) begin
1756 6 gdevic
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1757
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1758
                    ctl_alu_res_oe=1; /* Result latch */
1759
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1760
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1761
                    ctl_flags_xy_we=1;
1762
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
1763 8 gdevic
    if (M1 & T2) begin
1764 6 gdevic
                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
1765
                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
1766
                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
1767
                    ctl_flags_cf_we=1; ctl_flags_cf_cpl=1; /* CCF */
1768 8 gdevic
                    ctl_flags_hf_cpl=~flags_cf; /* Used for CCF */ end
1769
    if (M1 & T3) begin
1770 6 gdevic
                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
1771 8 gdevic
                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
1772 6 gdevic
                    ctl_flags_bus=1; /* Load FLAGT from the data bus */
1773 8 gdevic
                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
1774 6 gdevic
                    ctl_alu_op2_sel_bus=1; /* Internal bus */
1775
                    ctl_alu_op1_sel_bus=1; /* Internal bus */
1776
                    ctl_flags_sz_we=1;
1777
                    ctl_flags_xy_we=1;
1778
                    ctl_flags_hf_we=1;
1779
                    ctl_flags_pf_we=1;
1780
                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
1781
                    ctl_flags_cf_we=1; end
1782 8 gdevic
    if (M1 & T4) begin validPLA=1; setM1=1;
1783 6 gdevic
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1784
                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
1785
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1786
                    ctl_flags_xy_we=1;
1787
                    ctl_flags_hf_we=1;
1788
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
1789
end
1790
 
1791
if (pla[92]) begin
1792 8 gdevic
    if (M1 & T1) begin
1793 6 gdevic
                    ctl_flags_alu=1; /* Load FLAGT from the ALU */
1794
                    ctl_alu_oe=1; /* Enable ALU onto the data bus */
1795
                    ctl_alu_res_oe=1; /* Result latch */
1796
                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
1797
                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
1798
                    ctl_flags_xy_we=1;
1799
                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
1800 8 gdevic
    if (M1 & T2)