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[/] [a-z80/] [trunk/] [cpu/] [control/] [interrupts.v] - Blame information for rev 8

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1 3 gdevic
// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions 
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// and other software and tools, and its AMPP partner logic 
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// functions, and any output files from any of the foregoing 
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// (including device programming or simulation files), and any 
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// associated documentation or information are expressly subject 
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// to the terms and conditions of the Altera Program License 
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// Subscription Agreement, Altera MegaCore Function License 
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// Agreement, or other applicable license agreement, including, 
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// without limitation, that your use is for the sole purpose of 
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// programming logic devices manufactured by Altera and sold by 
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// Altera or its authorized distributors.  Please refer to the 
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// applicable agreement for further details.
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// PROGRAM              "Quartus II 64-Bit"
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// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
17 8 gdevic
// CREATED              "Sat Feb 13 19:23:03 2016"
18 3 gdevic
 
19
module interrupts(
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        ctl_iff1_iff2,
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        nmi,
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        setM1,
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        intr,
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        ctl_iffx_we,
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        ctl_iffx_bit,
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        ctl_im_we,
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        clk,
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        ctl_no_ints,
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        nreset,
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        db,
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        iff2,
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        im1,
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        im2,
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        in_nmi,
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        in_intr
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);
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38
 
39
input wire      ctl_iff1_iff2;
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input wire      nmi;
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input wire      setM1;
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input wire      intr;
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input wire      ctl_iffx_we;
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input wire      ctl_iffx_bit;
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input wire      ctl_im_we;
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input wire      clk;
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input wire      ctl_no_ints;
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input wire      nreset;
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input wire      [1:0] db;
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output wire     iff2;
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output reg      im1;
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output reg      im2;
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output wire     in_nmi;
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output wire     in_intr;
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56 8 gdevic
reg     iff1;
57 3 gdevic
wire    in_intr_ALTERA_SYNTHESIZED;
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reg     in_nmi_ALTERA_SYNTHESIZED;
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reg     int_armed;
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reg     nmi_armed;
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wire    test1;
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wire    SYNTHESIZED_WIRE_0;
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reg     DFFE_instIFF2;
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wire    SYNTHESIZED_WIRE_1;
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wire    SYNTHESIZED_WIRE_2;
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wire    SYNTHESIZED_WIRE_3;
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wire    SYNTHESIZED_WIRE_4;
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wire    SYNTHESIZED_WIRE_5;
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reg     DFFE_inst44;
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wire    SYNTHESIZED_WIRE_21;
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wire    SYNTHESIZED_WIRE_7;
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wire    SYNTHESIZED_WIRE_8;
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wire    SYNTHESIZED_WIRE_9;
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wire    SYNTHESIZED_WIRE_10;
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wire    SYNTHESIZED_WIRE_11;
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wire    SYNTHESIZED_WIRE_12;
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wire    SYNTHESIZED_WIRE_13;
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wire    SYNTHESIZED_WIRE_14;
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wire    SYNTHESIZED_WIRE_15;
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wire    SYNTHESIZED_WIRE_16;
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wire    SYNTHESIZED_WIRE_17;
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wire    SYNTHESIZED_WIRE_19;
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wire    SYNTHESIZED_WIRE_20;
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assign  iff2 = DFFE_instIFF2;
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assign  SYNTHESIZED_WIRE_10 = 1;
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88
 
89
 
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assign  SYNTHESIZED_WIRE_2 = ctl_iffx_bit & SYNTHESIZED_WIRE_0;
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assign  SYNTHESIZED_WIRE_1 = ctl_iff1_iff2 & DFFE_instIFF2;
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assign  SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
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assign  SYNTHESIZED_WIRE_17 = ctl_iffx_we | ctl_iff1_iff2;
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assign  SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_3 & nreset;
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assign  SYNTHESIZED_WIRE_0 =  ~ctl_iff1_iff2;
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assign  SYNTHESIZED_WIRE_4 =  ~db[0];
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assign  SYNTHESIZED_WIRE_5 =  ~in_nmi_ALTERA_SYNTHESIZED;
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assign  SYNTHESIZED_WIRE_20 = db[1] & db[0];
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assign  SYNTHESIZED_WIRE_19 = db[1] & SYNTHESIZED_WIRE_4;
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assign  in_intr_ALTERA_SYNTHESIZED = SYNTHESIZED_WIRE_5 & DFFE_inst44;
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assign  SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_7;
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115 8 gdevic
assign  SYNTHESIZED_WIRE_13 = iff1 & intr;
116 3 gdevic
 
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assign  test1 = setM1 & SYNTHESIZED_WIRE_8;
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always@(posedge nmi or negedge SYNTHESIZED_WIRE_9)
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begin
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if (!SYNTHESIZED_WIRE_9)
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        begin
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        nmi_armed <= 0;
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        end
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else
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        begin
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        nmi_armed <= SYNTHESIZED_WIRE_10;
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        end
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end
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assign  SYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_11 & nreset;
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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        begin
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        in_nmi_ALTERA_SYNTHESIZED <= 0;
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        end
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else
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if (test1)
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        begin
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        in_nmi_ALTERA_SYNTHESIZED <= nmi_armed;
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        end
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end
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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        begin
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        DFFE_inst44 <= 0;
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        end
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else
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if (test1)
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        begin
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        DFFE_inst44 <= int_armed;
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        end
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end
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always@(posedge clk or negedge SYNTHESIZED_WIRE_12)
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begin
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if (!SYNTHESIZED_WIRE_12)
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        begin
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        int_armed <= 0;
168
        end
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else
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        begin
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        int_armed <= SYNTHESIZED_WIRE_13;
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        end
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end
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assign  SYNTHESIZED_WIRE_9 = SYNTHESIZED_WIRE_14 & nreset;
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assign  SYNTHESIZED_WIRE_8 =  ~ctl_no_ints;
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179
 
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always@(posedge clk or negedge SYNTHESIZED_WIRE_15)
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begin
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if (!SYNTHESIZED_WIRE_15)
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        begin
184 8 gdevic
        iff1 <= 0;
185 3 gdevic
        end
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else
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if (SYNTHESIZED_WIRE_17)
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        begin
189 8 gdevic
        iff1 <= SYNTHESIZED_WIRE_16;
190 3 gdevic
        end
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end
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always@(posedge clk or negedge SYNTHESIZED_WIRE_21)
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begin
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if (!SYNTHESIZED_WIRE_21)
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        begin
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        DFFE_instIFF2 <= 0;
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        end
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else
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if (ctl_iffx_we)
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        begin
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        DFFE_instIFF2 <= ctl_iffx_bit;
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        end
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end
206
 
207
 
208
always@(posedge clk or negedge nreset)
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begin
210
if (!nreset)
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        begin
212
        im1 <= 0;
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        end
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else
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if (ctl_im_we)
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        begin
217
        im1 <= SYNTHESIZED_WIRE_19;
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        end
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end
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221
 
222
always@(posedge clk or negedge nreset)
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begin
224
if (!nreset)
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        begin
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        im2 <= 0;
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        end
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else
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if (ctl_im_we)
230
        begin
231
        im2 <= SYNTHESIZED_WIRE_20;
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        end
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end
234
 
235
assign  SYNTHESIZED_WIRE_3 =  ~in_intr_ALTERA_SYNTHESIZED;
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237
assign  SYNTHESIZED_WIRE_11 =  ~in_intr_ALTERA_SYNTHESIZED;
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239
assign  SYNTHESIZED_WIRE_7 =  ~in_nmi_ALTERA_SYNTHESIZED;
240
 
241
assign  SYNTHESIZED_WIRE_14 =  ~in_nmi_ALTERA_SYNTHESIZED;
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243
assign  in_nmi = in_nmi_ALTERA_SYNTHESIZED;
244
assign  in_intr = in_intr_ALTERA_SYNTHESIZED;
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endmodule

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