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// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.
 
// PROGRAM              "Quartus II 64-Bit"
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED              "Mon Dec 04 20:31:24 2017"
 
module memory_ifc(
        clk,
        nM1_int,
        ctl_mRead,
        ctl_mWrite,
        in_intr,
        nreset,
        fIORead,
        fIOWrite,
        setM1,
        ctl_iorw,
        timings_en,
        iorq_Tw,
        nhold_clk_wait,
        nM1_out,
        nRFSH_out,
        nMREQ_out,
        nRD_out,
        nWR_out,
        nIORQ_out,
        latch_wait,
        wait_m1
);
 
 
input wire      clk;
input wire      nM1_int;
input wire      ctl_mRead;
input wire      ctl_mWrite;
input wire      in_intr;
input wire      nreset;
input wire      fIORead;
input wire      fIOWrite;
input wire      setM1;
input wire      ctl_iorw;
input wire      timings_en;
input wire      iorq_Tw;
input wire      nhold_clk_wait;
output wire     nM1_out;
output wire     nRFSH_out;
output wire     nMREQ_out;
output wire     nRD_out;
output wire     nWR_out;
output wire     nIORQ_out;
output wire     latch_wait;
output wire     wait_m1;
 
wire    intr_iorq;
wire    ioRead;
wire    iorq;
wire    ioWrite;
wire    m1_mreq;
wire    mrd_mreq;
wire    mwr_mreq;
reg     mwr_wr;
wire    nMEMRQ_int;
wire    nq2;
reg     q1;
reg     q2;
wire    wait_io;
reg     wait_iorq;
reg     wait_iorqinta;
reg     wait_m_ALTERA_SYNTHESIZED1;
reg     wait_mrd;
reg     wait_mwr;
wire    SYNTHESIZED_WIRE_0;
reg     DFFE_m1_ff3;
wire    SYNTHESIZED_WIRE_1;
reg     DFFE_iorq_ff4;
reg     SYNTHESIZED_WIRE_15;
reg     DFFE_mrd_ff3;
reg     DFFE_intr_ff3;
wire    SYNTHESIZED_WIRE_2;
reg     SYNTHESIZED_WIRE_16;
wire    SYNTHESIZED_WIRE_3;
reg     SYNTHESIZED_WIRE_17;
wire    SYNTHESIZED_WIRE_18;
reg     DFFE_iorq_ff1;
reg     DFFE_m1_ff1;
reg     DFFE_mrd_ff1;
reg     DFFE_mwr_ff1;
reg     DFFE_mreq_ff2;
 
 
 
 
assign  nMREQ_out = SYNTHESIZED_WIRE_0 & nMEMRQ_int;
 
assign  ioRead = iorq & fIORead;
 
assign  SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m_ALTERA_SYNTHESIZED1);
 
assign  m1_mreq = ~(in_intr | SYNTHESIZED_WIRE_1);
 
assign  iorq = wait_iorq | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_15;
 
assign  ioWrite = iorq & fIOWrite;
 
assign  latch_wait = wait_mrd | wait_io | wait_m_ALTERA_SYNTHESIZED1 | wait_mwr;
 
assign  nMEMRQ_int = ~(m1_mreq | mrd_mreq | mwr_mreq);
 
assign  nRD_out = ~(m1_mreq | mrd_mreq | ioRead);
 
assign  mrd_mreq = DFFE_mrd_ff3 | wait_mrd;
 
assign  nWR_out = ~(ioWrite | mwr_wr);
 
assign  mwr_mreq = mwr_wr | wait_mwr;
 
assign  nIORQ_out = ~(intr_iorq | iorq);
 
assign  wait_io = wait_iorqinta | wait_iorq;
 
assign  intr_iorq = DFFE_intr_ff3 | wait_iorqinta;
 
assign  nM1_out = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_16;
 
assign  SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_17);
 
assign  nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_16);
 
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
        begin
        wait_iorqinta <= 0;
        end
else
if (timings_en)
        begin
        wait_iorqinta <= iorq_Tw;
        end
end
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        DFFE_intr_ff3 <= 0;
        end
else
if (nhold_clk_wait)
        begin
        DFFE_intr_ff3 <= wait_iorqinta;
        end
end
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        DFFE_iorq_ff1 <= 0;
        end
else
if (timings_en)
        begin
        DFFE_iorq_ff1 <= ctl_iorw;
        end
end
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        SYNTHESIZED_WIRE_15 <= 0;
        end
else
if (timings_en)
        begin
        SYNTHESIZED_WIRE_15 <= DFFE_iorq_ff1;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
        begin
        wait_iorq <= 0;
        end
else
if (timings_en)
        begin
        wait_iorq <= SYNTHESIZED_WIRE_15;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
        begin
        DFFE_iorq_ff4 <= 0;
        end
else
if (timings_en)
        begin
        DFFE_iorq_ff4 <= wait_iorq;
        end
end
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        SYNTHESIZED_WIRE_16 <= 0;
        end
else
if (timings_en)
        begin
        SYNTHESIZED_WIRE_16 <= nM1_int;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
        begin
        DFFE_m1_ff1 <= 1;
        end
else
if (timings_en)
        begin
        DFFE_m1_ff1 <= setM1;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
        begin
        wait_m_ALTERA_SYNTHESIZED1 <= 0;
        end
else
if (timings_en)
        begin
        wait_m_ALTERA_SYNTHESIZED1 <= DFFE_m1_ff1;
        end
end
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        DFFE_m1_ff3 <= 0;
        end
else
if (timings_en)
        begin
        DFFE_m1_ff3 <= wait_m_ALTERA_SYNTHESIZED1;
        end
end
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        DFFE_mrd_ff1 <= 0;
        end
else
if (timings_en)
        begin
        DFFE_mrd_ff1 <= ctl_mRead;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
        begin
        wait_mrd <= 0;
        end
else
if (timings_en)
        begin
        wait_mrd <= DFFE_mrd_ff1;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
        begin
        DFFE_mrd_ff3 <= 0;
        end
else
if (timings_en)
        begin
        DFFE_mrd_ff3 <= wait_mrd;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
        begin
        SYNTHESIZED_WIRE_17 <= 0;
        end
else
if (timings_en)
        begin
        SYNTHESIZED_WIRE_17 <= SYNTHESIZED_WIRE_16;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
        begin
        DFFE_mreq_ff2 <= 0;
        end
else
if (timings_en)
        begin
        DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_17;
        end
end
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        DFFE_mwr_ff1 <= 0;
        end
else
if (timings_en)
        begin
        DFFE_mwr_ff1 <= ctl_mWrite;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
        begin
        wait_mwr <= 0;
        end
else
if (timings_en)
        begin
        wait_mwr <= DFFE_mwr_ff1;
        end
end
 
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
begin
if (!nreset)
        begin
        mwr_wr <= 0;
        end
else
if (timings_en)
        begin
        mwr_wr <= wait_mwr;
        end
end
 
assign  SYNTHESIZED_WIRE_18 =  ~clk;
 
assign  nq2 =  ~q2;
 
assign  SYNTHESIZED_WIRE_2 =  ~nreset;
 
assign  SYNTHESIZED_WIRE_3 =  ~DFFE_mreq_ff2;
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        q1 <= 0;
        end
else
if (timings_en)
        begin
        q1 <= SYNTHESIZED_WIRE_16;
        end
end
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        q2 <= 0;
        end
else
if (timings_en)
        begin
        q2 <= q1;
        end
end
 
assign  wait_m1 = wait_m_ALTERA_SYNTHESIZED1;
 
endmodule

Line No.	Rev	Author	Line
1	3	gdevic	`// Copyright (C) 1991-2013 Altera Corporation`
2			`// Your use of Altera Corporation's design tools, logic functions`
3			`// and other software and tools, and its AMPP partner logic`
4			`// functions, and any output files from any of the foregoing`
5			`// (including device programming or simulation files), and any`
6			`// associated documentation or information are expressly subject`
7			`// to the terms and conditions of the Altera Program License`
8			`// Subscription Agreement, Altera MegaCore Function License`
9			`// Agreement, or other applicable license agreement, including,`
10			`// without limitation, that your use is for the sole purpose of`
11			`// programming logic devices manufactured by Altera and sold by`
12			`// Altera or its authorized distributors. Please refer to the`
13			`// applicable agreement for further details.`
14
15			`// PROGRAM "Quartus II 64-Bit"`
16			`// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"`
17	18	gdevic	`// CREATED "Mon Dec 04 20:31:24 2017"`
18	3	gdevic
19			`module memory_ifc(`
20			`clk,`
21			`nM1_int,`
22			`ctl_mRead,`
23			`ctl_mWrite,`
24			`in_intr,`
25			`nreset,`
26			`fIORead,`
27			`fIOWrite,`
28			`setM1,`
29			`ctl_iorw,`
30			`timings_en,`
31			`iorq_Tw,`
32	16	gdevic	`nhold_clk_wait,`
33	3	gdevic	`nM1_out,`
34			`nRFSH_out,`
35			`nMREQ_out,`
36			`nRD_out,`
37			`nWR_out,`
38			`nIORQ_out,`
39	13	gdevic	`latch_wait,`
40			`wait_m1`
41	3	gdevic	`);`
42
43
44			`input wire clk;`
45			`input wire nM1_int;`
46			`input wire ctl_mRead;`
47			`input wire ctl_mWrite;`
48			`input wire in_intr;`
49			`input wire nreset;`
50			`input wire fIORead;`
51			`input wire fIOWrite;`
52			`input wire setM1;`
53			`input wire ctl_iorw;`
54			`input wire timings_en;`
55			`input wire iorq_Tw;`
56	16	gdevic	`input wire nhold_clk_wait;`
57	3	gdevic	`output wire nM1_out;`
58			`output wire nRFSH_out;`
59			`output wire nMREQ_out;`
60			`output wire nRD_out;`
61			`output wire nWR_out;`
62			`output wire nIORQ_out;`
63			`output wire latch_wait;`
64	13	gdevic	`output wire wait_m1;`
65	3	gdevic
66			`wire intr_iorq;`
67			`wire ioRead;`
68			`wire iorq;`
69			`wire ioWrite;`
70			`wire m1_mreq;`
71			`wire mrd_mreq;`
72			`wire mwr_mreq;`
73			`reg mwr_wr;`
74			`wire nMEMRQ_int;`
75			`wire nq2;`
76			`reg q1;`
77			`reg q2;`
78	18	gdevic	`wire wait_io;`
79	3	gdevic	`reg wait_iorq;`
80	18	gdevic	`reg wait_iorqinta;`
81	13	gdevic	`reg wait_m_ALTERA_SYNTHESIZED1;`
82	3	gdevic	`reg wait_mrd;`
83			`reg wait_mwr;`
84			`wire SYNTHESIZED_WIRE_0;`
85			`reg DFFE_m1_ff3;`
86			`wire SYNTHESIZED_WIRE_1;`
87	18	gdevic	`reg DFFE_iorq_ff4;`
88	16	gdevic	`reg SYNTHESIZED_WIRE_15;`
89	3	gdevic	`reg DFFE_mrd_ff3;`
90			`reg DFFE_intr_ff3;`
91			`wire SYNTHESIZED_WIRE_2;`
92	18	gdevic	`reg SYNTHESIZED_WIRE_16;`
93			`wire SYNTHESIZED_WIRE_3;`
94	16	gdevic	`reg SYNTHESIZED_WIRE_17;`
95	18	gdevic	`wire SYNTHESIZED_WIRE_18;`
96	3	gdevic	`reg DFFE_iorq_ff1;`
97			`reg DFFE_m1_ff1;`
98			`reg DFFE_mrd_ff1;`
99			`reg DFFE_mwr_ff1;`
100			`reg DFFE_mreq_ff2;`
101
102
103
104
105			`assign nMREQ_out = SYNTHESIZED_WIRE_0 & nMEMRQ_int;`
106
107			`assign ioRead = iorq & fIORead;`
108
109	13	gdevic	`assign SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 \| wait_m_ALTERA_SYNTHESIZED1);`
110	3	gdevic
111			`assign m1_mreq = ~(in_intr \| SYNTHESIZED_WIRE_1);`
112
113	18	gdevic	`assign iorq = wait_iorq \| DFFE_iorq_ff4 \| SYNTHESIZED_WIRE_15;`
114	3	gdevic
115			`assign ioWrite = iorq & fIOWrite;`
116
117	18	gdevic	`assign latch_wait = wait_mrd \| wait_io \| wait_m_ALTERA_SYNTHESIZED1 \| wait_mwr;`
118	3	gdevic
119			`assign nMEMRQ_int = ~(m1_mreq \| mrd_mreq \| mwr_mreq);`
120
121			`assign nRD_out = ~(m1_mreq \| mrd_mreq \| ioRead);`
122
123			`assign mrd_mreq = DFFE_mrd_ff3 \| wait_mrd;`
124
125			`assign nWR_out = ~(ioWrite \| mwr_wr);`
126
127			`assign mwr_mreq = mwr_wr \| wait_mwr;`
128
129			`assign nIORQ_out = ~(intr_iorq \| iorq);`
130
131	18	gdevic	`assign wait_io = wait_iorqinta \| wait_iorq;`
132	3	gdevic
133	18	gdevic	`assign intr_iorq = DFFE_intr_ff3 \| wait_iorqinta;`
134	3	gdevic
135	18	gdevic	`assign nM1_out = SYNTHESIZED_WIRE_2 \| SYNTHESIZED_WIRE_16;`
136	13	gdevic
137	18	gdevic	`assign SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_17);`
138	3	gdevic
139	18	gdevic	`assign nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_16);`
140	3	gdevic
141	18	gdevic
142			`always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)`
143	3	gdevic	`begin`
144			`if (!nreset)`
145			`begin`
146	18	gdevic	`wait_iorqinta <= 0;`
147	3	gdevic	`end`
148			`else`
149	18	gdevic	`if (timings_en)`
150	3	gdevic	`begin`
151	18	gdevic	`wait_iorqinta <= iorq_Tw;`
152	3	gdevic	`end`
153			`end`
154
155
156			`always@(posedge clk or negedge nreset)`
157			`begin`
158			`if (!nreset)`
159			`begin`
160			`DFFE_intr_ff3 <= 0;`
161			`end`
162			`else`
163	16	gdevic	`if (nhold_clk_wait)`
164	3	gdevic	`begin`
165	18	gdevic	`DFFE_intr_ff3 <= wait_iorqinta;`
166	3	gdevic	`end`
167			`end`
168
169
170			`always@(posedge clk or negedge nreset)`
171			`begin`
172			`if (!nreset)`
173			`begin`
174			`DFFE_iorq_ff1 <= 0;`
175			`end`
176			`else`
177			`if (timings_en)`
178			`begin`
179			`DFFE_iorq_ff1 <= ctl_iorw;`
180			`end`
181			`end`
182
183
184			`always@(posedge clk or negedge nreset)`
185			`begin`
186			`if (!nreset)`
187			`begin`
188	18	gdevic	`SYNTHESIZED_WIRE_15 <= 0;`
189	3	gdevic	`end`
190			`else`
191			`if (timings_en)`
192			`begin`
193	18	gdevic	`SYNTHESIZED_WIRE_15 <= DFFE_iorq_ff1;`
194	3	gdevic	`end`
195			`end`
196
197
198	18	gdevic	`always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)`
199	3	gdevic	`begin`
200			`if (!nreset)`
201			`begin`
202	18	gdevic	`wait_iorq <= 0;`
203	3	gdevic	`end`
204			`else`
205			`if (timings_en)`
206			`begin`
207	18	gdevic	`wait_iorq <= SYNTHESIZED_WIRE_15;`
208	3	gdevic	`end`
209			`end`
210
211
212	18	gdevic	`always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)`
213	3	gdevic	`begin`
214			`if (!nreset)`
215			`begin`
216			`DFFE_iorq_ff4 <= 0;`
217			`end`
218			`else`
219			`if (timings_en)`
220			`begin`
221	18	gdevic	`DFFE_iorq_ff4 <= wait_iorq;`
222	3	gdevic	`end`
223			`end`
224
225
226			`always@(posedge clk or negedge nreset)`
227			`begin`
228			`if (!nreset)`
229			`begin`
230	18	gdevic	`SYNTHESIZED_WIRE_16 <= 0;`
231	3	gdevic	`end`
232			`else`
233			`if (timings_en)`
234			`begin`
235	18	gdevic	`SYNTHESIZED_WIRE_16 <= nM1_int;`
236	3	gdevic	`end`
237			`end`
238
239
240	18	gdevic	`always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)`
241	3	gdevic	`begin`
242			`if (!nreset)`
243			`begin`
244			`DFFE_m1_ff1 <= 1;`
245			`end`
246			`else`
247			`if (timings_en)`
248			`begin`
249			`DFFE_m1_ff1 <= setM1;`
250			`end`
251			`end`
252
253
254	18	gdevic	`always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)`
255	3	gdevic	`begin`
256			`if (!nreset)`
257			`begin`
258	13	gdevic	`wait_m_ALTERA_SYNTHESIZED1 <= 0;`
259	3	gdevic	`end`
260			`else`
261			`if (timings_en)`
262			`begin`
263	13	gdevic	`wait_m_ALTERA_SYNTHESIZED1 <= DFFE_m1_ff1;`
264	3	gdevic	`end`
265			`end`
266
267
268			`always@(posedge clk or negedge nreset)`
269			`begin`
270			`if (!nreset)`
271			`begin`
272			`DFFE_m1_ff3 <= 0;`
273			`end`
274			`else`
275			`if (timings_en)`
276			`begin`
277	13	gdevic	`DFFE_m1_ff3 <= wait_m_ALTERA_SYNTHESIZED1;`
278	3	gdevic	`end`
279			`end`
280
281
282			`always@(posedge clk or negedge nreset)`
283			`begin`
284			`if (!nreset)`
285			`begin`
286			`DFFE_mrd_ff1 <= 0;`
287			`end`
288			`else`
289			`if (timings_en)`
290			`begin`
291			`DFFE_mrd_ff1 <= ctl_mRead;`
292			`end`
293			`end`
294
295
296	18	gdevic	`always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)`
297	3	gdevic	`begin`
298			`if (!nreset)`
299			`begin`
300			`wait_mrd <= 0;`
301			`end`
302			`else`
303			`if (timings_en)`
304			`begin`
305			`wait_mrd <= DFFE_mrd_ff1;`
306			`end`
307			`end`
308
309
310	18	gdevic	`always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)`
311	3	gdevic	`begin`
312			`if (!nreset)`
313			`begin`
314			`DFFE_mrd_ff3 <= 0;`
315			`end`
316			`else`
317			`if (timings_en)`
318			`begin`
319			`DFFE_mrd_ff3 <= wait_mrd;`
320			`end`
321			`end`
322
323
324	18	gdevic	`always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)`
325	3	gdevic	`begin`
326			`if (!nreset)`
327			`begin`
328	18	gdevic	`SYNTHESIZED_WIRE_17 <= 0;`
329	3	gdevic	`end`
330			`else`
331			`if (timings_en)`
332			`begin`
333	18	gdevic	`SYNTHESIZED_WIRE_17 <= SYNTHESIZED_WIRE_16;`
334	3	gdevic	`end`
335			`end`
336
337
338	18	gdevic	`always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)`
339	3	gdevic	`begin`
340			`if (!nreset)`
341			`begin`
342			`DFFE_mreq_ff2 <= 0;`
343			`end`
344			`else`
345			`if (timings_en)`
346			`begin`
347	18	gdevic	`DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_17;`
348	3	gdevic	`end`
349			`end`
350
351
352			`always@(posedge clk or negedge nreset)`
353			`begin`
354			`if (!nreset)`
355			`begin`
356			`DFFE_mwr_ff1 <= 0;`
357			`end`
358			`else`
359			`if (timings_en)`
360			`begin`
361			`DFFE_mwr_ff1 <= ctl_mWrite;`
362			`end`
363			`end`
364
365
366	18	gdevic	`always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)`
367	3	gdevic	`begin`
368			`if (!nreset)`
369			`begin`
370			`wait_mwr <= 0;`
371			`end`
372			`else`
373			`if (timings_en)`
374			`begin`
375			`wait_mwr <= DFFE_mwr_ff1;`
376			`end`
377			`end`
378
379
380	18	gdevic	`always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)`
381	3	gdevic	`begin`
382			`if (!nreset)`
383			`begin`
384			`mwr_wr <= 0;`
385			`end`
386			`else`
387			`if (timings_en)`
388			`begin`
389			`mwr_wr <= wait_mwr;`
390			`end`
391			`end`
392
393	18	gdevic	`assign SYNTHESIZED_WIRE_18 = ~clk;`
394	3	gdevic
395			`assign nq2 = ~q2;`
396
397	13	gdevic	`assign SYNTHESIZED_WIRE_2 = ~nreset;`
398	3	gdevic
399	13	gdevic	`assign SYNTHESIZED_WIRE_3 = ~DFFE_mreq_ff2;`
400	3	gdevic
401	13	gdevic
402	3	gdevic	`always@(posedge clk or negedge nreset)`
403			`begin`
404			`if (!nreset)`
405			`begin`
406			`q1 <= 0;`
407			`end`
408			`else`
409			`if (timings_en)`
410			`begin`
411	18	gdevic	`q1 <= SYNTHESIZED_WIRE_16;`
412	3	gdevic	`end`
413			`end`
414
415
416			`always@(posedge clk or negedge nreset)`
417			`begin`
418			`if (!nreset)`
419			`begin`
420			`q2 <= 0;`
421			`end`
422			`else`
423			`if (timings_en)`
424			`begin`
425			`q2 <= q1;`
426			`end`
427			`end`
428
429	13	gdevic	`assign wait_m1 = wait_m_ALTERA_SYNTHESIZED1;`
430	3	gdevic
431			`endmodule`

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