OpenCores
URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

Subversion Repositories a-z80

[/] [a-z80/] [trunk/] [cpu/] [control/] [resets.bsf] - Blame information for rev 16

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 gdevic
/*
2
WARNING: Do NOT edit the input and output ports in this file in a text
3
editor if you plan to continue editing the block that represents it in
4
the Block Editor! File corruption is VERY likely to occur.
5
*/
6
/*
7
Copyright (C) 1991-2013 Altera Corporation
8
Your use of Altera Corporation's design tools, logic functions
9
and other software and tools, and its AMPP partner logic
10
functions, and any output files from any of the foregoing
11
(including device programming or simulation files), and any
12
associated documentation or information are expressly subject
13
to the terms and conditions of the Altera Program License
14
Subscription Agreement, Altera MegaCore Function License
15
Agreement, or other applicable license agreement, including,
16
without limitation, that your use is for the sole purpose of
17
programming logic devices manufactured by Altera and sold by
18
Altera or its authorized distributors.  Please refer to the
19
applicable agreement for further details.
20
*/
21
(header "symbol" (version "1.2"))
22
(symbol
23 16 gdevic
        (rect 16 16 192 176)
24 3 gdevic
        (text "resets" (rect 5 0 41 14)(font "Arial" (font_size 8)))
25 13 gdevic
        (text "inst" (rect 8 144 25 156)(font "Arial" ))
26 3 gdevic
        (port
27
                (pt 0 32)
28
                (input)
29
                (text "fpga_reset" (rect 0 0 62 14)(font "Arial" (font_size 8)))
30
                (text "fpga_reset" (rect 21 27 83 41)(font "Arial" (font_size 8)))
31
                (line (pt 0 32)(pt 16 32))
32
        )
33
        (port
34
                (pt 0 48)
35
                (input)
36
                (text "reset_in" (rect 0 0 46 14)(font "Arial" (font_size 8)))
37
                (text "reset_in" (rect 21 43 67 57)(font "Arial" (font_size 8)))
38
                (line (pt 0 48)(pt 16 48))
39
        )
40
        (port
41
                (pt 0 64)
42
                (input)
43
                (text "M1" (rect 0 0 16 14)(font "Arial" (font_size 8)))
44
                (text "M1" (rect 21 59 37 73)(font "Arial" (font_size 8)))
45
                (line (pt 0 64)(pt 16 64))
46
        )
47
        (port
48
                (pt 0 80)
49
                (input)
50
                (text "T2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
51
                (text "T2" (rect 21 75 35 89)(font "Arial" (font_size 8)))
52
                (line (pt 0 80)(pt 16 80))
53
        )
54
        (port
55
                (pt 0 96)
56
                (input)
57
                (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
58
                (text "clk" (rect 21 91 36 105)(font "Arial" (font_size 8)))
59
                (line (pt 0 96)(pt 16 96))
60
        )
61
        (port
62 13 gdevic
                (pt 0 112)
63
                (input)
64 16 gdevic
                (text "nhold_clk_wait" (rect 0 0 84 14)(font "Arial" (font_size 8)))
65
                (text "nhold_clk_wait" (rect 21 107 105 121)(font "Arial" (font_size 8)))
66 13 gdevic
                (line (pt 0 112)(pt 16 112))
67 3 gdevic
        )
68
        (port
69 16 gdevic
                (pt 176 32)
70 3 gdevic
                (output)
71
                (text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
72 16 gdevic
                (text "nreset" (rect 119 27 155 41)(font "Arial" (font_size 8)))
73
                (line (pt 176 32)(pt 160 32))
74 3 gdevic
        )
75 13 gdevic
        (port
76 16 gdevic
                (pt 176 48)
77 13 gdevic
                (output)
78
                (text "clrpc" (rect 0 0 28 14)(font "Arial" (font_size 8)))
79 16 gdevic
                (text "clrpc" (rect 127 43 155 57)(font "Arial" (font_size 8)))
80
                (line (pt 176 48)(pt 160 48))
81 13 gdevic
        )
82 3 gdevic
        (drawing
83 16 gdevic
                (rectangle (rect 16 16 160 144))
84 3 gdevic
        )
85
)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.