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gdevic |
; Copyright 1991-2009 Mentor Graphics Corporation
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;
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; All Rights Reserved.
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;
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gdevic |
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
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gdevic |
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
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gdevic |
;
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gdevic |
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[Library]
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std = $MODEL_TECH/../std
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ieee = $MODEL_TECH/../ieee
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verilog = $MODEL_TECH/../verilog
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vital2000 = $MODEL_TECH/../vital2000
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std_developerskit = $MODEL_TECH/../std_developerskit
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synopsys = $MODEL_TECH/../synopsys
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modelsim_lib = $MODEL_TECH/../modelsim_lib
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sv_std = $MODEL_TECH/../sv_std
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; Altera Primitive libraries
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;
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; VHDL Section
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;
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altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
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altera = $MODEL_TECH/../altera/vhdl/altera
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altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
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lpm = $MODEL_TECH/../altera/vhdl/220model
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220model = $MODEL_TECH/../altera/vhdl/220model
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max = $MODEL_TECH/../altera/vhdl/max
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maxii = $MODEL_TECH/../altera/vhdl/maxii
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maxv = $MODEL_TECH/../altera/vhdl/maxv
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stratix = $MODEL_TECH/../altera/vhdl/stratix
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stratixii = $MODEL_TECH/../altera/vhdl/stratixii
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stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx
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hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii
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hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii
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hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv
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cyclone = $MODEL_TECH/../altera/vhdl/cyclone
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cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
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cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii
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cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils
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sgate = $MODEL_TECH/../altera/vhdl/sgate
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stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx
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altgxb = $MODEL_TECH/../altera/vhdl/altgxb
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stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb
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stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi
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arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi
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arriaii = $MODEL_TECH/../altera/vhdl/arriaii
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arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
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arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
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arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
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arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
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arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
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arriagx = $MODEL_TECH/../altera/vhdl/arriagx
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altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb
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stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
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stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
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stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
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cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
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cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
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cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
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cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
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hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi
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hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip
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stratixv = $MODEL_TECH/../altera/vhdl/stratixv
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stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
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stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
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arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
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arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
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arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
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arriav = $MODEL_TECH/../altera/vhdl/arriav
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cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
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;
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; Verilog Section
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;
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altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
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altera_ver = $MODEL_TECH/../altera/verilog/altera
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altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
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lpm_ver = $MODEL_TECH/../altera/verilog/220model
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220model_ver = $MODEL_TECH/../altera/verilog/220model
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max_ver = $MODEL_TECH/../altera/verilog/max
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maxii_ver = $MODEL_TECH/../altera/verilog/maxii
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maxv_ver = $MODEL_TECH/../altera/verilog/maxv
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stratix_ver = $MODEL_TECH/../altera/verilog/stratix
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stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
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stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx
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arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx
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hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii
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hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii
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hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv
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cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
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cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
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cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii
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cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils
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sgate_ver = $MODEL_TECH/../altera/verilog/sgate
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stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx
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altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb
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stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb
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stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi
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arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi
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arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
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arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
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arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
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arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
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arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
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arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
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stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
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stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
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stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
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stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
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stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
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stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
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stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
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stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
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arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
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arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
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arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
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arriav_ver = $MODEL_TECH/../altera/verilog/arriav
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arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
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arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
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cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
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cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
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cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
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cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
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cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
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cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
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cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
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hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi
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hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip
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work = work
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[vcom]
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8 |
gdevic |
; VHDL93 variable selects language version as the default.
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3 |
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; Default is VHDL-2002.
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; Value of 0 or 1987 for VHDL-1987.
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; Value of 1 or 1993 for VHDL-1993.
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; Default or value of 2 or 2002 for VHDL-2002.
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; Default or value of 3 or 2008 for VHDL-2008.
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VHDL93 = 2002
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; Show source line containing error. Default is off.
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; Show_source = 1
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; Turn off unbound-component warnings. Default is on.
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; Show_Warning1 = 0
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; Turn off process-without-a-wait-statement warnings. Default is on.
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; Show_Warning2 = 0
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; Turn off null-range warnings. Default is on.
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; Show_Warning3 = 0
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; Turn off no-space-in-time-literal warnings. Default is on.
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; Show_Warning4 = 0
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; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
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; Show_Warning5 = 0
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; Turn off optimization for IEEE std_logic_1164 package. Default is on.
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; Optimize_1164 = 0
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; Turn on resolving of ambiguous function overloading in favor of the
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; "explicit" function declaration (not the one automatically created by
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; the compiler for each type declaration). Default is off.
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; The .ini file has Explicit enabled so that std_logic_signed/unsigned
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; will match the behavior of synthesis tools.
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Explicit = 1
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; Turn off acceleration of the VITAL packages. Default is to accelerate.
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; NoVital = 1
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; Turn off VITAL compliance checking. Default is checking on.
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; NoVitalCheck = 1
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; Ignore VITAL compliance checking errors. Default is to not ignore.
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; IgnoreVitalErrors = 1
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; Turn off VITAL compliance checking warnings. Default is to show warnings.
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; Show_VitalChecksWarnings = 0
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; Keep silent about case statement static warnings.
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; Default is to give a warning.
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; NoCaseStaticError = 1
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; Keep silent about warnings caused by aggregates that are not locally static.
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; Default is to give a warning.
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; NoOthersStaticError = 1
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; Turn off inclusion of debugging info within design units.
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; Default is to include debugging info.
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; NoDebug = 1
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; Turn off "Loading..." messages. Default is messages on.
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; Quiet = 1
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; Turn on some limited synthesis rule compliance checking. Checks only:
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; -- signals used (read) by a process must be in the sensitivity list
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; CheckSynthesis = 1
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; Activate optimizations on expressions that do not involve signals,
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; waits, or function/procedure/task invocations. Default is off.
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; ScalarOpts = 1
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; Require the user to specify a configuration for all bindings,
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; and do not generate a compile time default binding for the
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; component. This will result in an elaboration error of
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; 'component not bound' if the user fails to do so. Avoids the rare
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; issue of a false dependency upon the unused default binding.
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; RequireConfigForAllDefaultBinding = 1
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; Inhibit range checking on subscripts of arrays. Range checking on
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; scalars defined with subtypes is inhibited by default.
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; NoIndexCheck = 1
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; Inhibit range checks on all (implicit and explicit) assignments to
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; scalar objects defined with subtypes.
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; NoRangeCheck = 1
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[vlog]
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219 |
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220 |
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; Turn off inclusion of debugging info within design units.
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; Default is to include debugging info.
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; NoDebug = 1
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; Turn off "loading..." messages. Default is messages on.
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; Quiet = 1
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; Turn on Verilog hazard checking (order-dependent accessing of global vars).
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; Default is off.
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; Hazard = 1
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; Turn on converting regular Verilog identifiers to uppercase. Allows case
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; insensitivity for module names. Default is no conversion.
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; UpCase = 1
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; Turn on incremental compilation of modules. Default is off.
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; Incremental = 1
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; Turns on lint-style checking.
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; Show_Lint = 1
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[vsim]
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242 |
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; Simulator resolution
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; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
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Resolution = ps
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; User time unit for run commands
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; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
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; unit specified for Resolution. For example, if Resolution is 100ps,
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; then UserTimeUnit defaults to ps.
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; Should generally be set to default.
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UserTimeUnit = default
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; Default run length
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RunLength = 0 ns
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; Maximum iterations that can be run without advancing simulation time
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IterationLimit = 5000
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; Directive to license manager:
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; vhdl Immediately reserve a VHDL license
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; vlog Immediately reserve a Verilog license
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; plus Immediately reserve a VHDL and Verilog license
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263 |
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; nomgc Do not look for Mentor Graphics Licenses
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264 |
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; nomti Do not look for Model Technology Licenses
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265 |
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; noqueue Do not wait in the license queue when a license isn't available
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266 |
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; viewsim Try for viewer license but accept simulator license(s) instead
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267 |
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; of queuing for viewer license
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; License = plus
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269 |
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; Stop the simulator after a VHDL/Verilog assertion message
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; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
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BreakOnAssertion = 4
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; Assertion Message Format
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275 |
8 |
gdevic |
; %S - Severity Level
|
276 |
3 |
gdevic |
; %R - Report Message
|
277 |
|
|
; %T - Time of assertion
|
278 |
|
|
; %D - Delta
|
279 |
|
|
; %I - Instance or Region pathname (if available)
|
280 |
|
|
; %% - print '%' character
|
281 |
|
|
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
282 |
|
|
|
283 |
|
|
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
|
284 |
|
|
; AssertFile = assert.log
|
285 |
|
|
|
286 |
|
|
; Default radix for all windows and commands...
|
287 |
|
|
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
288 |
|
|
DefaultRadix = symbolic
|
289 |
|
|
|
290 |
|
|
; VSIM Startup command
|
291 |
|
|
; Startup = do startup.do
|
292 |
|
|
|
293 |
|
|
; File for saving command transcript
|
294 |
|
|
TranscriptFile = transcript
|
295 |
|
|
|
296 |
|
|
; File for saving command history
|
297 |
|
|
; CommandHistory = cmdhist.log
|
298 |
|
|
|
299 |
|
|
; Specify whether paths in simulator commands should be described
|
300 |
|
|
; in VHDL or Verilog format.
|
301 |
|
|
; For VHDL, PathSeparator = /
|
302 |
|
|
; For Verilog, PathSeparator = .
|
303 |
|
|
; Must not be the same character as DatasetSeparator.
|
304 |
|
|
PathSeparator = /
|
305 |
|
|
|
306 |
|
|
; Specify the dataset separator for fully rooted contexts.
|
307 |
|
|
; The default is ':'. For example, sim:/top
|
308 |
|
|
; Must not be the same character as PathSeparator.
|
309 |
|
|
DatasetSeparator = :
|
310 |
|
|
|
311 |
|
|
; Disable VHDL assertion messages
|
312 |
|
|
; IgnoreNote = 1
|
313 |
|
|
; IgnoreWarning = 1
|
314 |
|
|
; IgnoreError = 1
|
315 |
|
|
; IgnoreFailure = 1
|
316 |
|
|
|
317 |
|
|
; Default force kind. May be freeze, drive, deposit, or default
|
318 |
|
|
; or in other terms, fixed, wired, or charged.
|
319 |
|
|
; A value of "default" will use the signal kind to determine the
|
320 |
|
|
; force kind, drive for resolved signals, freeze for unresolved signals
|
321 |
|
|
; DefaultForceKind = freeze
|
322 |
|
|
|
323 |
|
|
; If zero, open files when elaborated; otherwise, open files on
|
324 |
|
|
; first read or write. Default is 0.
|
325 |
|
|
; DelayFileOpen = 1
|
326 |
|
|
|
327 |
|
|
; Control VHDL files opened for write.
|
328 |
|
|
; 0 = Buffered, 1 = Unbuffered
|
329 |
|
|
UnbufferedOutput = 0
|
330 |
|
|
|
331 |
|
|
; Control the number of VHDL files open concurrently.
|
332 |
|
|
; This number should always be less than the current ulimit
|
333 |
|
|
; setting for max file descriptors.
|
334 |
|
|
; 0 = unlimited
|
335 |
|
|
ConcurrentFileLimit = 40
|
336 |
|
|
|
337 |
|
|
; Control the number of hierarchical regions displayed as
|
338 |
|
|
; part of a signal name shown in the Wave window.
|
339 |
|
|
; A value of zero tells VSIM to display the full name.
|
340 |
|
|
; The default is 0.
|
341 |
|
|
; WaveSignalNameWidth = 0
|
342 |
|
|
|
343 |
|
|
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
344 |
|
|
; and std_logic_signed packages.
|
345 |
|
|
; StdArithNoWarnings = 1
|
346 |
|
|
|
347 |
|
|
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
|
348 |
|
|
; NumericStdNoWarnings = 1
|
349 |
|
|
|
350 |
|
|
; Control the format of the (VHDL) FOR generate statement label
|
351 |
|
|
; for each iteration. Do not quote it.
|
352 |
|
|
; The format string here must contain the conversion codes %s and %d,
|
353 |
|
|
; in that order, and no other conversion codes. The %s represents
|
354 |
|
|
; the generate_label; the %d represents the generate parameter value
|
355 |
|
|
; at a particular generate iteration (this is the position number if
|
356 |
|
|
; the generate parameter is of an enumeration type). Embedded whitespace
|
357 |
|
|
; is allowed (but discouraged); leading and trailing whitespace is ignored.
|
358 |
|
|
; Application of the format must result in a unique scope name over all
|
359 |
|
|
; such names in the design so that name lookup can function properly.
|
360 |
|
|
; GenerateFormat = %s__%d
|
361 |
|
|
|
362 |
|
|
; Specify whether checkpoint files should be compressed.
|
363 |
|
|
; The default is 1 (compressed).
|
364 |
|
|
; CheckpointCompressMode = 0
|
365 |
|
|
|
366 |
|
|
; List of dynamically loaded objects for Verilog PLI applications
|
367 |
|
|
; Veriuser = veriuser.sl
|
368 |
|
|
|
369 |
|
|
; Specify default options for the restart command. Options can be one
|
370 |
|
|
; or more of: -force -nobreakpoint -nolist -nolog -nowave
|
371 |
|
|
; DefaultRestartOptions = -force
|
372 |
|
|
|
373 |
|
|
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
374 |
|
|
; (> 500 megabyte memory footprint). Default is disabled.
|
375 |
|
|
; Specify number of megabytes to lock.
|
376 |
|
|
; LockedMemory = 1000
|
377 |
|
|
|
378 |
|
|
; Turn on (1) or off (0) WLF file compression.
|
379 |
|
|
; The default is 1 (compress WLF file).
|
380 |
|
|
; WLFCompress = 0
|
381 |
|
|
|
382 |
|
|
; Specify whether to save all design hierarchy (1) in the WLF file
|
383 |
|
|
; or only regions containing logged signals (0).
|
384 |
|
|
; The default is 0 (save only regions with logged signals).
|
385 |
|
|
; WLFSaveAllRegions = 1
|
386 |
|
|
|
387 |
|
|
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
388 |
|
|
; to the specified amount of simulation time. When the limit is exceeded
|
389 |
|
|
; the earliest times get truncated from the file.
|
390 |
|
|
; If both time and size limits are specified the most restrictive is used.
|
391 |
|
|
; UserTimeUnits are used if time units are not specified.
|
392 |
|
|
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
|
393 |
|
|
; WLFTimeLimit = 0
|
394 |
|
|
|
395 |
|
|
; WLF file size limit. Limit WLF file size, as closely as possible,
|
396 |
|
|
; to the specified number of megabytes. If both time and size limits
|
397 |
|
|
; are specified then the most restrictive is used.
|
398 |
|
|
; The default is 0 (no limit).
|
399 |
|
|
; WLFSizeLimit = 1000
|
400 |
|
|
|
401 |
|
|
; Specify whether or not a WLF file should be deleted when the
|
402 |
|
|
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
403 |
|
|
; The default is 0 (do not delete WLF file when simulation ends).
|
404 |
|
|
; WLFDeleteOnQuit = 1
|
405 |
|
|
|
406 |
|
|
; Automatic SDF compilation
|
407 |
|
|
; Disables automatic compilation of SDF files in flows that support it.
|
408 |
|
|
; Default is on, uncomment to turn off.
|
409 |
|
|
; NoAutoSDFCompile = 1
|
410 |
|
|
|
411 |
|
|
DelayFileOpen = 1
|
412 |
|
|
[lmc]
|
413 |
|
|
|
414 |
|
|
[msg_system]
|
415 |
|
|
; Change a message severity or suppress a message.
|
416 |
|
|
; The format is: = [,...]
|
417 |
|
|
; Examples:
|
418 |
|
|
; note = 3009
|
419 |
|
|
; warning = 3033
|
420 |
|
|
; error = 3010,3016
|
421 |
|
|
; fatal = 3016,3033
|
422 |
|
|
; suppress = 3009,3016,3043
|
423 |
|
|
; The command verror can be used to get the complete
|
424 |
|
|
; description of a message.
|
425 |
|
|
|
426 |
|
|
; Control transcripting of elaboration/runtime messages.
|
427 |
8 |
gdevic |
; The default is to have messages appear in the transcript and
|
428 |
3 |
gdevic |
; recorded in the wlf file (messages that are recorded in the
|
429 |
|
|
; wlf file can be viewed in the MsgViewer). The other settings
|
430 |
8 |
gdevic |
; are to send messages only to the transcript or only to the
|
431 |
3 |
gdevic |
; wlf file. The valid values are
|
432 |
|
|
; both {default}
|
433 |
|
|
; tran {transcript only}
|
434 |
|
|
; wlf {wlf file only}
|
435 |
|
|
; msgmode = both
|
436 |
|
|
[Project]
|
437 |
|
|
; Warning -- Do not edit the project properties directly.
|
438 |
|
|
; Property names are dynamic in nature and property
|
439 |
|
|
; values have special syntax. Changing property data directly
|
440 |
|
|
; can result in a corrupt MPF file. All project properties
|
441 |
|
|
; can be modified through project window dialogs.
|
442 |
|
|
Project_Version = 6
|
443 |
|
|
Project_DefaultLib = work
|
444 |
|
|
Project_SortMethod = unused
|
445 |
6 |
gdevic |
Project_Files_Count = 8
|
446 |
3 |
gdevic |
Project_File_0 = $ROOT/cpu/control/interrupts.v
|
447 |
|
|
Project_File_P_0 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder interrupts group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
448 |
|
|
Project_File_1 = $ROOT/cpu/control/pin_control.v
|
449 |
|
|
Project_File_P_1 = compile_order 6 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {pin control} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
450 |
|
|
Project_File_2 = $ROOT/cpu/control/resets.v
|
451 |
|
|
Project_File_P_2 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder reset group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
452 |
6 |
gdevic |
Project_File_3 = $ROOT/cpu/control/sequencer.v
|
453 |
|
|
Project_File_P_3 = compile_order 7 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder sequencer group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
454 |
|
|
Project_File_4 = $ROOT/cpu/control/test_interrupts.sv
|
455 |
|
|
Project_File_P_4 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder interrupts group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
456 |
|
|
Project_File_5 = $ROOT/cpu/control/test_pin_control.sv
|
457 |
|
|
Project_File_P_5 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {pin control} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
458 |
|
|
Project_File_6 = $ROOT/cpu/control/test_reset.sv
|
459 |
|
|
Project_File_P_6 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder reset group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
460 |
|
|
Project_File_7 = $ROOT/cpu/control/test_sequencer.sv
|
461 |
|
|
Project_File_P_7 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder sequencer group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
462 |
3 |
gdevic |
Project_Sim_Count = 4
|
463 |
|
|
Project_Sim_0 = Test pin control
|
464 |
|
|
Project_Sim_P_0 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {pin control} +pulse_e {} additional_dus work.test_pin_control -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
|
465 |
|
|
Project_Sim_1 = Test interrupts
|
466 |
|
|
Project_Sim_P_1 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder interrupts +pulse_e {} additional_dus work.test_interrupts -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
|
467 |
|
|
Project_Sim_2 = Test reset
|
468 |
|
|
Project_Sim_P_2 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder reset +pulse_e {} additional_dus work.test_reset -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
|
469 |
|
|
Project_Sim_3 = Test sequencer
|
470 |
|
|
Project_Sim_P_3 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder sequencer +pulse_e {} additional_dus work.test_sequencer -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
|
471 |
|
|
Project_Folder_Count = 4
|
472 |
|
|
Project_Folder_0 = interrupts
|
473 |
|
|
Project_Folder_P_0 = folder {Top Level}
|
474 |
|
|
Project_Folder_1 = pin control
|
475 |
|
|
Project_Folder_P_1 = folder {Top Level}
|
476 |
|
|
Project_Folder_2 = reset
|
477 |
|
|
Project_Folder_P_2 = folder {Top Level}
|
478 |
|
|
Project_Folder_3 = sequencer
|
479 |
|
|
Project_Folder_P_3 = folder {Top Level}
|
480 |
|
|
Echo_Compile_Output = 0
|
481 |
|
|
Save_Compile_Report = 1
|
482 |
|
|
Project_Opt_Count = 0
|
483 |
|
|
ForceSoftPaths = 1
|
484 |
|
|
ProjectStatusDelay = 5000
|
485 |
|
|
VERILOG_DoubleClick = Edit
|
486 |
8 |
gdevic |
VERILOG_CustomDoubleClick =
|
487 |
3 |
gdevic |
SYSTEMVERILOG_DoubleClick = Edit
|
488 |
8 |
gdevic |
SYSTEMVERILOG_CustomDoubleClick =
|
489 |
3 |
gdevic |
VHDL_DoubleClick = Edit
|
490 |
8 |
gdevic |
VHDL_CustomDoubleClick =
|
491 |
3 |
gdevic |
PSL_DoubleClick = Edit
|
492 |
8 |
gdevic |
PSL_CustomDoubleClick =
|
493 |
3 |
gdevic |
TEXT_DoubleClick = Edit
|
494 |
8 |
gdevic |
TEXT_CustomDoubleClick =
|
495 |
3 |
gdevic |
SYSTEMC_DoubleClick = Edit
|
496 |
8 |
gdevic |
SYSTEMC_CustomDoubleClick =
|
497 |
3 |
gdevic |
TCL_DoubleClick = Edit
|
498 |
8 |
gdevic |
TCL_CustomDoubleClick =
|
499 |
3 |
gdevic |
MACRO_DoubleClick = Edit
|
500 |
8 |
gdevic |
MACRO_CustomDoubleClick =
|
501 |
3 |
gdevic |
VCD_DoubleClick = Edit
|
502 |
8 |
gdevic |
VCD_CustomDoubleClick =
|
503 |
3 |
gdevic |
SDF_DoubleClick = Edit
|
504 |
8 |
gdevic |
SDF_CustomDoubleClick =
|
505 |
3 |
gdevic |
XML_DoubleClick = Edit
|
506 |
8 |
gdevic |
XML_CustomDoubleClick =
|
507 |
3 |
gdevic |
LOGFILE_DoubleClick = Edit
|
508 |
8 |
gdevic |
LOGFILE_CustomDoubleClick =
|
509 |
3 |
gdevic |
UCDB_DoubleClick = Edit
|
510 |
8 |
gdevic |
UCDB_CustomDoubleClick =
|
511 |
3 |
gdevic |
UPF_DoubleClick = Edit
|
512 |
8 |
gdevic |
UPF_CustomDoubleClick =
|
513 |
3 |
gdevic |
PCF_DoubleClick = Edit
|
514 |
8 |
gdevic |
PCF_CustomDoubleClick =
|
515 |
3 |
gdevic |
PROJECT_DoubleClick = Edit
|
516 |
8 |
gdevic |
PROJECT_CustomDoubleClick =
|
517 |
3 |
gdevic |
VRM_DoubleClick = Edit
|
518 |
8 |
gdevic |
VRM_CustomDoubleClick =
|
519 |
3 |
gdevic |
DEBUGDATABASE_DoubleClick = Edit
|
520 |
8 |
gdevic |
DEBUGDATABASE_CustomDoubleClick =
|
521 |
3 |
gdevic |
DEBUGARCHIVE_DoubleClick = Edit
|
522 |
8 |
gdevic |
DEBUGARCHIVE_CustomDoubleClick =
|
523 |
3 |
gdevic |
Project_Major_Version = 10
|
524 |
|
|
Project_Minor_Version = 1
|