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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 1991-2013 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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*/
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(text "reg_sw_4d_hi" (rect 0 0 82 14)(font "Arial" (font_size 8)))
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3 |
gdevic |
(line (pt 264 336)(pt 248 336))
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312 |
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)
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(port
|
314 |
|
|
(pt 264 352)
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315 |
|
|
(output)
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316 |
8 |
gdevic |
(text "reg_sel_ir" (rect 0 0 56 14)(font "Arial" (font_size 8)))
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317 |
|
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(text "reg_sel_ir" (rect 187 347 243 361)(font "Arial" (font_size 8)))
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gdevic |
(line (pt 264 352)(pt 248 352))
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319 |
|
|
)
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320 |
8 |
gdevic |
(port
|
321 |
|
|
(pt 264 368)
|
322 |
|
|
(output)
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323 |
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(text "reg_sel_pc" (rect 0 0 63 14)(font "Arial" (font_size 8)))
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324 |
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(text "reg_sel_pc" (rect 180 363 243 377)(font "Arial" (font_size 8)))
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(line (pt 264 368)(pt 248 368))
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326 |
|
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)
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327 |
|
|
(port
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328 |
|
|
(pt 264 384)
|
329 |
|
|
(output)
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330 |
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(text "reg_sel_wz" (rect 0 0 68 14)(font "Arial" (font_size 8)))
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331 |
|
|
(text "reg_sel_wz" (rect 175 379 243 393)(font "Arial" (font_size 8)))
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332 |
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(line (pt 264 384)(pt 248 384))
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333 |
|
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)
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3 |
gdevic |
(drawing
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gdevic |
(rectangle (rect 16 16 248 400))
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336 |
3 |
gdevic |
)
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337 |
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)
|