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[/] [a-z80/] [trunk/] [cpu/] [registers/] [test_latch.sv] - Blame information for rev 3

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1 3 gdevic
//==============================================================
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// Test 8-bit latch block
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//==============================================================
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`timescale 100 ns/ 100 ns
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module test_latch;
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// ----------------- CLOCKS AND RESET -----------------
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// Define one full T-clock cycle delay
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`define T #2
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bit clk = 1;
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initial repeat (30) #1 clk = ~clk;
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// ----------------------------------------------------
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// Bi-directional bus with 3-state
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reg  [7:0] db;              // Drive it using these wires
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wire [7:0] db_sig;          // Read it using these wires
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reg oe_sig;
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reg we_sig;
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// ----------------- TEST -------------------
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`define CHECK(arg) \
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   assert(db_sig===arg);
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initial begin
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    oe_sig = 0;
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    we_sig = 0;
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    // Test bidirectional data bus and leave it at Z
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    `T  db = 8'hAA;
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    `T  db = 'z;
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    `T `CHECK(8'hz);
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    // Write a byte into the latch
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    `T  db = 8'h55;
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    `T  we_sig = 1;
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    `T  we_sig = 0;
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    `T  db = 'z;
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    // Read latch
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    `T  db = 'z;
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    `T  oe_sig = 1;
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    `T `CHECK(8'h55);
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    `T  oe_sig = 0;
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    `T  $display("End of test");
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end
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// Drive a 3-state bidirectional bus with this statement
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assign db_sig = db;
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//--------------------------------------------------------------
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// Instantiate register latch
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//--------------------------------------------------------------
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reg_latch reg_latch_inst
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(
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    .clk(clk),
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    .oe(oe_sig) ,               // input  oe_sig
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    .we(we_sig) ,               // input  we_sig
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    .db(db_sig[7:0])            // inout [7:0] db_sig
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);
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endmodule

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