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[/] [a-z80/] [trunk/] [cpu/] [toplevel/] [globals.vh] - Blame information for rev 16

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Line No. Rev Author Line
1 6 gdevic
// Automatically generated by genglobals.py
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// Module: control/clk_delay.v
4
wire hold_clk_iorq;
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wire hold_clk_wait;
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wire iorq_Tw;
7
wire busack;
8
wire pin_control_oe;
9
wire hold_clk_busrq;
10 16 gdevic
wire nhold_clk_wait;
11 6 gdevic
 
12
// Module: control/decode_state.v
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wire in_halt;
14
wire table_cb;
15
wire table_ed;
16
wire table_xx;
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wire use_ix;
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wire use_ixiy;
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wire in_alu;
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wire repeat_en;
21
 
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// Module: control/exec_module.vh
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wire ctl_state_iy_set;
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wire ctl_state_ixiy_clr;
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wire ctl_state_ixiy_we;
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wire ctl_state_halt_set;
27
wire ctl_state_tbl_ed_set;
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wire ctl_state_tbl_cb_set;
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wire ctl_state_alu;
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wire ctl_repeat_we;
31 13 gdevic
wire ctl_state_tbl_we;
32 6 gdevic
wire ctl_iff1_iff2;
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wire ctl_iffx_we;
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wire ctl_iffx_bit;
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wire ctl_im_we;
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wire ctl_no_ints;
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wire ctl_ir_we;
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wire ctl_mRead;
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wire ctl_mWrite;
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wire ctl_iorw;
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wire ctl_shift_en;
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wire ctl_daa_oe;
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wire ctl_alu_op_low;
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wire ctl_cond_short;
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wire ctl_alu_core_hf;
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wire ctl_eval_cond;
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wire ctl_66_oe;
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wire [1:0] ctl_pf_sel;
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wire ctl_alu_oe;
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wire ctl_alu_shift_oe;
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wire ctl_alu_op2_oe;
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wire ctl_alu_res_oe;
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wire ctl_alu_op1_oe;
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wire ctl_alu_bs_oe;
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wire ctl_alu_op1_sel_bus;
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wire ctl_alu_op1_sel_low;
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wire ctl_alu_op1_sel_zero;
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wire ctl_alu_op2_sel_zero;
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wire ctl_alu_op2_sel_bus;
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wire ctl_alu_op2_sel_lq;
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wire ctl_alu_sel_op2_neg;
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wire ctl_alu_sel_op2_high;
63
wire ctl_alu_core_R;
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wire ctl_alu_core_V;
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wire ctl_alu_core_S;
66
wire ctl_flags_oe;
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wire ctl_flags_bus;
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wire ctl_flags_alu;
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wire ctl_flags_nf_set;
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wire ctl_flags_cf_set;
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wire ctl_flags_cf_cpl;
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wire ctl_flags_cf_we;
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wire ctl_flags_sz_we;
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wire ctl_flags_xy_we;
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wire ctl_flags_hf_we;
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wire ctl_flags_pf_we;
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wire ctl_flags_nf_we;
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wire ctl_flags_cf2_we;
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wire ctl_flags_hf_cpl;
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wire ctl_flags_use_cf2;
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wire ctl_flags_hf2_we;
82
wire ctl_flags_nf_clr;
83
wire ctl_alu_zero_16bit;
84 8 gdevic
wire ctl_flags_cf2_sel_shift;
85
wire ctl_flags_cf2_sel_daa;
86 6 gdevic
wire ctl_sw_4u;
87
wire ctl_reg_in_hi;
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wire ctl_reg_in_lo;
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wire ctl_reg_out_lo;
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wire ctl_reg_out_hi;
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wire ctl_reg_exx;
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wire ctl_reg_ex_af;
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wire ctl_reg_ex_de_hl;
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wire ctl_reg_use_sp;
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wire ctl_reg_sel_pc;
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wire ctl_reg_sel_ir;
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wire ctl_reg_sel_wz;
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wire ctl_reg_gp_we;
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wire ctl_reg_not_pc;
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wire ctl_reg_sys_we_lo;
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wire ctl_reg_sys_we_hi;
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wire ctl_reg_sys_we;
103 8 gdevic
wire ctl_sw_4d;
104 6 gdevic
wire [1:0] ctl_reg_gp_hilo;
105
wire [1:0] ctl_reg_gp_sel;
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wire [1:0] ctl_reg_sys_hilo;
107
wire ctl_inc_cy;
108
wire ctl_inc_dec;
109
wire ctl_al_we;
110
wire ctl_inc_limit6;
111
wire ctl_bus_inc_oe;
112
wire ctl_apin_mux;
113
wire ctl_apin_mux2;
114
wire ctl_bus_ff_oe;
115
wire ctl_bus_zero_oe;
116
wire ctl_sw_1u;
117
wire ctl_sw_1d;
118
wire ctl_sw_2u;
119
wire ctl_sw_2d;
120
wire ctl_sw_mask543_en;
121
wire ctl_bus_db_we;
122 8 gdevic
wire ctl_bus_db_oe;
123 6 gdevic
 
124 8 gdevic
// Module: control/execute.v
125 6 gdevic
wire nextM;
126
wire setM1;
127
wire fFetch;
128
wire fMRead;
129
wire fMWrite;
130
wire fIORead;
131
wire fIOWrite;
132
 
133
// Module: control/interrupts.v
134
wire iff2;
135
wire im1;
136
wire im2;
137
wire in_nmi;
138
wire in_intr;
139
 
140
// Module: control/ir.v
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wire [7:0] opcode;
142
 
143
// Module: control/pin_control.v
144
wire bus_ab_pin_we;
145
wire bus_db_pin_oe;
146
wire bus_db_pin_re;
147
 
148 8 gdevic
// Module: control/pla_decode.v
149 6 gdevic
wire [104:0] pla;
150
 
151
// Module: control/resets.v
152
wire clrpc;
153
wire nreset;
154
 
155
// Module: control/memory_ifc.v
156
wire nM1_out;
157
wire nRFSH_out;
158
wire nMREQ_out;
159
wire nRD_out;
160
wire nWR_out;
161
wire nIORQ_out;
162
wire latch_wait;
163 13 gdevic
wire wait_m1;
164 6 gdevic
 
165
// Module: control/sequencer.v
166
wire M1;
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wire M2;
168
wire M3;
169
wire M4;
170
wire M5;
171
wire T1;
172
wire T2;
173
wire T3;
174
wire T4;
175
wire T5;
176
wire T6;
177
wire timings_en;
178
 
179
// Module: alu/alu_control.v
180
wire alu_shift_in;
181
wire alu_shift_right;
182
wire alu_shift_left;
183
wire shift_cf_out;
184
wire alu_parity_in;
185
wire flags_cond_true;
186
wire daa_cf_out;
187
wire pf_sel;
188
wire alu_op_low;
189
wire alu_core_cf_in;
190
wire [7:0] db;
191
 
192
// Module: alu/alu_select.v
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wire alu_oe;
194
wire alu_shift_oe;
195
wire alu_op2_oe;
196
wire alu_res_oe;
197
wire alu_op1_oe;
198
wire alu_bs_oe;
199
wire alu_op1_sel_bus;
200
wire alu_op1_sel_low;
201
wire alu_op1_sel_zero;
202
wire alu_op2_sel_zero;
203
wire alu_op2_sel_bus;
204
wire alu_op2_sel_lq;
205
wire alu_sel_op2_neg;
206
wire alu_sel_op2_high;
207
wire alu_core_R;
208
wire alu_core_V;
209
wire alu_core_S;
210
 
211
// Module: alu/alu_flags.v
212
wire flags_sf;
213
wire flags_zf;
214
wire flags_hf;
215
wire flags_pf;
216
wire flags_cf;
217
wire flags_nf;
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wire flags_cf_latch;
219
wire flags_hf2;
220
 
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// Module: alu/alu.v
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wire alu_zero;
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wire alu_parity_out;
224
wire alu_high_eq_9;
225
wire alu_high_gt_9;
226
wire alu_low_gt_9;
227
wire alu_shift_db0;
228
wire alu_shift_db7;
229
wire alu_core_cf_out;
230
wire alu_sf_out;
231
wire alu_yf_out;
232
wire alu_xf_out;
233
wire alu_vf_out;
234
wire [3:0] test_db_high;
235
wire [3:0] test_db_low;
236
 
237
// Module: registers/reg_control.v
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wire reg_sel_bc;
239
wire reg_sel_bc2;
240
wire reg_sel_ix;
241
wire reg_sel_iy;
242
wire reg_sel_de;
243
wire reg_sel_hl;
244
wire reg_sel_de2;
245
wire reg_sel_hl2;
246
wire reg_sel_af;
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wire reg_sel_af2;
248
wire reg_sel_wz;
249
wire reg_sel_pc;
250
wire reg_sel_ir;
251
wire reg_sel_sp;
252
wire reg_sel_gp_hi;
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wire reg_sel_gp_lo;
254
wire reg_sel_sys_lo;
255
wire reg_sel_sys_hi;
256
wire reg_gp_we;
257
wire reg_sys_we_lo;
258
wire reg_sys_we_hi;
259 8 gdevic
wire reg_sw_4d_lo;
260
wire reg_sw_4d_hi;
261 6 gdevic
 
262
// Module: bus/address_latch.v
263
wire address_is_1;
264
wire [15:0] address;
265
 
266
// Module: bus/address_pins.v
267
wire [15:0] abus;
268
 
269 8 gdevic
// Module: bus/bus_switch.v
270 6 gdevic
wire bus_sw_1u;
271
wire bus_sw_1d;
272
wire bus_sw_2u;
273
wire bus_sw_2d;
274
wire bus_sw_mask543_en;
275
 
276
// Module: bus/control_pins_n.v
277
wire nmi;
278
wire busrq;
279
wire clk;
280
wire intr;
281
wire mwait;
282
wire reset_in;
283
wire pin_nM1;
284
wire pin_nMREQ;
285
wire pin_nIORQ;
286
wire pin_nRD;
287
wire pin_nWR;
288
wire pin_nRFSH;
289
wire pin_nHALT;
290
wire pin_nBUSACK;

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