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URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

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[/] [a-z80/] [trunk/] [cpu/] [toplevel/] [test_fuse.vh] - Blame information for rev 6

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Line No. Rev Author Line
1 6 gdevic
// Automatically generated by genfuse.py
2
 
3
force dut.reg_file_.reg_gp_we=0;
4
force dut.reg_control_.ctl_reg_sys_we=0;
5
force dut.z80_top_ifc_n.fpga_reset=1;
6
#2
7
//--------------------------------------------------------------------------------
8
   force dut.instruction_reg_.ctl_ir_we=1;
9
   force dut.instruction_reg_.db=0;
10
#2 release dut.instruction_reg_.ctl_ir_we;
11
   release dut.instruction_reg_.db;
12
$fdisplay(f,"Testing opcode 00      NOP");
13
   // Preset af
14
   force dut.reg_file_.b2v_latch_af_lo.we=1;
15
   force dut.reg_file_.b2v_latch_af_hi.we=1;
16
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
17
   force dut.reg_file_.b2v_latch_af_hi.db=8'h00;
18
#2 release dut.reg_file_.b2v_latch_af_lo.we;
19
   release dut.reg_file_.b2v_latch_af_hi.we;
20
   release dut.reg_file_.b2v_latch_af_lo.db;
21
   release dut.reg_file_.b2v_latch_af_hi.db;
22
   // Preset bc
23
   force dut.reg_file_.b2v_latch_bc_lo.we=1;
24
   force dut.reg_file_.b2v_latch_bc_hi.we=1;
25
   force dut.reg_file_.b2v_latch_bc_lo.db=8'h00;
26
   force dut.reg_file_.b2v_latch_bc_hi.db=8'h00;
27
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
28
   release dut.reg_file_.b2v_latch_bc_hi.we;
29
   release dut.reg_file_.b2v_latch_bc_lo.db;
30
   release dut.reg_file_.b2v_latch_bc_hi.db;
31
   // Preset de
32
   force dut.reg_file_.b2v_latch_de_lo.we=1;
33
   force dut.reg_file_.b2v_latch_de_hi.we=1;
34
   force dut.reg_file_.b2v_latch_de_lo.db=8'h00;
35
   force dut.reg_file_.b2v_latch_de_hi.db=8'h00;
36
#2 release dut.reg_file_.b2v_latch_de_lo.we;
37
   release dut.reg_file_.b2v_latch_de_hi.we;
38
   release dut.reg_file_.b2v_latch_de_lo.db;
39
   release dut.reg_file_.b2v_latch_de_hi.db;
40
   // Preset hl
41
   force dut.reg_file_.b2v_latch_hl_lo.we=1;
42
   force dut.reg_file_.b2v_latch_hl_hi.we=1;
43
   force dut.reg_file_.b2v_latch_hl_lo.db=8'h00;
44
   force dut.reg_file_.b2v_latch_hl_hi.db=8'h00;
45
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
46
   release dut.reg_file_.b2v_latch_hl_hi.we;
47
   release dut.reg_file_.b2v_latch_hl_lo.db;
48
   release dut.reg_file_.b2v_latch_hl_hi.db;
49
   // Preset af2
50
   force dut.reg_file_.b2v_latch_af2_lo.we=1;
51
   force dut.reg_file_.b2v_latch_af2_hi.we=1;
52
   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
53
   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
54
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
55
   release dut.reg_file_.b2v_latch_af2_hi.we;
56
   release dut.reg_file_.b2v_latch_af2_lo.db;
57
   release dut.reg_file_.b2v_latch_af2_hi.db;
58
   // Preset bc2
59
   force dut.reg_file_.b2v_latch_bc2_lo.we=1;
60
   force dut.reg_file_.b2v_latch_bc2_hi.we=1;
61
   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
62
   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
63
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
64
   release dut.reg_file_.b2v_latch_bc2_hi.we;
65
   release dut.reg_file_.b2v_latch_bc2_lo.db;
66
   release dut.reg_file_.b2v_latch_bc2_hi.db;
67
   // Preset de2
68
   force dut.reg_file_.b2v_latch_de2_lo.we=1;
69
   force dut.reg_file_.b2v_latch_de2_hi.we=1;
70
   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
71
   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
72
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
73
   release dut.reg_file_.b2v_latch_de2_hi.we;
74
   release dut.reg_file_.b2v_latch_de2_lo.db;
75
   release dut.reg_file_.b2v_latch_de2_hi.db;
76
   // Preset hl2
77
   force dut.reg_file_.b2v_latch_hl2_lo.we=1;
78
   force dut.reg_file_.b2v_latch_hl2_hi.we=1;
79
   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
80
   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
81
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
82
   release dut.reg_file_.b2v_latch_hl2_hi.we;
83
   release dut.reg_file_.b2v_latch_hl2_lo.db;
84
   release dut.reg_file_.b2v_latch_hl2_hi.db;
85
   // Preset ix
86
   force dut.reg_file_.b2v_latch_ix_lo.we=1;
87
   force dut.reg_file_.b2v_latch_ix_hi.we=1;
88
   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
89
   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
90
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
91
   release dut.reg_file_.b2v_latch_ix_hi.we;
92
   release dut.reg_file_.b2v_latch_ix_lo.db;
93
   release dut.reg_file_.b2v_latch_ix_hi.db;
94
   // Preset iy
95
   force dut.reg_file_.b2v_latch_iy_lo.we=1;
96
   force dut.reg_file_.b2v_latch_iy_hi.we=1;
97
   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
98
   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
99
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
100
   release dut.reg_file_.b2v_latch_iy_hi.we;
101
   release dut.reg_file_.b2v_latch_iy_lo.db;
102
   release dut.reg_file_.b2v_latch_iy_hi.db;
103
   // Preset sp
104
   force dut.reg_file_.b2v_latch_sp_lo.we=1;
105
   force dut.reg_file_.b2v_latch_sp_hi.we=1;
106
   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
107
   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
108
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
109
   release dut.reg_file_.b2v_latch_sp_hi.we;
110
   release dut.reg_file_.b2v_latch_sp_lo.db;
111
   release dut.reg_file_.b2v_latch_sp_hi.db;
112
   // Preset wz
113
   force dut.reg_file_.b2v_latch_wz_lo.we=1;
114
   force dut.reg_file_.b2v_latch_wz_hi.we=1;
115
   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
116
   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
117
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
118
   release dut.reg_file_.b2v_latch_wz_hi.we;
119
   release dut.reg_file_.b2v_latch_wz_lo.db;
120
   release dut.reg_file_.b2v_latch_wz_hi.db;
121
   // Preset pc
122
   force dut.reg_file_.b2v_latch_pc_lo.we=1;
123
   force dut.reg_file_.b2v_latch_pc_hi.we=1;
124
   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
125
   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
126
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
127
   release dut.reg_file_.b2v_latch_pc_hi.we;
128
   release dut.reg_file_.b2v_latch_pc_lo.db;
129
   release dut.reg_file_.b2v_latch_pc_hi.db;
130
   // Preset ir
131
   force dut.reg_file_.b2v_latch_ir_lo.we=1;
132
   force dut.reg_file_.b2v_latch_ir_hi.we=1;
133
   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
134
   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
135
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
136
   release dut.reg_file_.b2v_latch_ir_hi.we;
137
   release dut.reg_file_.b2v_latch_ir_lo.db;
138
   release dut.reg_file_.b2v_latch_ir_hi.db;
139
   // Preset memory
140
   ram.Mem[0] = 8'h00;
141
   force dut.z80_top_ifc_n.fpga_reset=0;
142
   force dut.address_latch_.abus=16'h0000;
143
   release dut.reg_control_.ctl_reg_sys_we;
144
   release dut.reg_file_.reg_gp_we;
145
#3
146
   release dut.address_latch_.abus;
147
#1
148
#6 // Execute
149
   force dut.reg_control_.ctl_reg_sys_we=0;
150
#2 pc=z.A;
151
#2
152
#1 force dut.reg_file_.reg_gp_we=0;
153
   force dut.z80_top_ifc_n.fpga_reset=1;
154
   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch);
155
   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h00) $fdisplay(f,"* Reg af a=%h !=00",dut.reg_file_.b2v_latch_af_hi.latch);
156
   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h00) $fdisplay(f,"* Reg bc c=%h !=00",dut.reg_file_.b2v_latch_bc_lo.latch);
157
   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h00) $fdisplay(f,"* Reg bc b=%h !=00",dut.reg_file_.b2v_latch_bc_hi.latch);
158
   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,"* Reg de e=%h !=00",dut.reg_file_.b2v_latch_de_lo.latch);
159
   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,"* Reg de d=%h !=00",dut.reg_file_.b2v_latch_de_hi.latch);
160
   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h00) $fdisplay(f,"* Reg hl l=%h !=00",dut.reg_file_.b2v_latch_hl_lo.latch);
161
   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h00) $fdisplay(f,"* Reg hl h=%h !=00",dut.reg_file_.b2v_latch_hl_hi.latch);
162
   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
163
   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
164
   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
165
   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
166
   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
167
   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
168
   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
169
   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
170
   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
171
   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
172
   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
173
   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
174
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
175
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
176
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
177
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
178
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
179
//--------------------------------------------------------------------------------
180
   force dut.instruction_reg_.ctl_ir_we=1;
181
   force dut.instruction_reg_.db=0;
182
#2 release dut.instruction_reg_.ctl_ir_we;
183
   release dut.instruction_reg_.db;
184
$fdisplay(f,"Testing opcode ed67    RRD");
185
   // Preset af
186
   force dut.reg_file_.b2v_latch_af_lo.we=1;
187
   force dut.reg_file_.b2v_latch_af_hi.we=1;
188
   force dut.reg_file_.b2v_latch_af_lo.db=8'h24;
189
   force dut.reg_file_.b2v_latch_af_hi.db=8'h36;
190
#2 release dut.reg_file_.b2v_latch_af_lo.we;
191
   release dut.reg_file_.b2v_latch_af_hi.we;
192
   release dut.reg_file_.b2v_latch_af_lo.db;
193
   release dut.reg_file_.b2v_latch_af_hi.db;
194
   // Preset bc
195
   force dut.reg_file_.b2v_latch_bc_lo.we=1;
196
   force dut.reg_file_.b2v_latch_bc_hi.we=1;
197
   force dut.reg_file_.b2v_latch_bc_lo.db=8'h6a;
198
   force dut.reg_file_.b2v_latch_bc_hi.db=8'hb1;
199
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
200
   release dut.reg_file_.b2v_latch_bc_hi.we;
201
   release dut.reg_file_.b2v_latch_bc_lo.db;
202
   release dut.reg_file_.b2v_latch_bc_hi.db;
203
   // Preset de
204
   force dut.reg_file_.b2v_latch_de_lo.we=1;
205
   force dut.reg_file_.b2v_latch_de_hi.we=1;
206
   force dut.reg_file_.b2v_latch_de_lo.db=8'hdb;
207
   force dut.reg_file_.b2v_latch_de_hi.db=8'ha4;
208
#2 release dut.reg_file_.b2v_latch_de_lo.we;
209
   release dut.reg_file_.b2v_latch_de_hi.we;
210
   release dut.reg_file_.b2v_latch_de_lo.db;
211
   release dut.reg_file_.b2v_latch_de_hi.db;
212
   // Preset hl
213
   force dut.reg_file_.b2v_latch_hl_lo.we=1;
214
   force dut.reg_file_.b2v_latch_hl_hi.we=1;
215
   force dut.reg_file_.b2v_latch_hl_lo.db=8'hde;
216
   force dut.reg_file_.b2v_latch_hl_hi.db=8'hb9;
217
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
218
   release dut.reg_file_.b2v_latch_hl_hi.we;
219
   release dut.reg_file_.b2v_latch_hl_lo.db;
220
   release dut.reg_file_.b2v_latch_hl_hi.db;
221
   // Preset af2
222
   force dut.reg_file_.b2v_latch_af2_lo.we=1;
223
   force dut.reg_file_.b2v_latch_af2_hi.we=1;
224
   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
225
   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
226
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
227
   release dut.reg_file_.b2v_latch_af2_hi.we;
228
   release dut.reg_file_.b2v_latch_af2_lo.db;
229
   release dut.reg_file_.b2v_latch_af2_hi.db;
230
   // Preset bc2
231
   force dut.reg_file_.b2v_latch_bc2_lo.we=1;
232
   force dut.reg_file_.b2v_latch_bc2_hi.we=1;
233
   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
234
   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
235
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
236
   release dut.reg_file_.b2v_latch_bc2_hi.we;
237
   release dut.reg_file_.b2v_latch_bc2_lo.db;
238
   release dut.reg_file_.b2v_latch_bc2_hi.db;
239
   // Preset de2
240
   force dut.reg_file_.b2v_latch_de2_lo.we=1;
241
   force dut.reg_file_.b2v_latch_de2_hi.we=1;
242
   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
243
   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
244
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
245
   release dut.reg_file_.b2v_latch_de2_hi.we;
246
   release dut.reg_file_.b2v_latch_de2_lo.db;
247
   release dut.reg_file_.b2v_latch_de2_hi.db;
248
   // Preset hl2
249
   force dut.reg_file_.b2v_latch_hl2_lo.we=1;
250
   force dut.reg_file_.b2v_latch_hl2_hi.we=1;
251
   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
252
   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
253
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
254
   release dut.reg_file_.b2v_latch_hl2_hi.we;
255
   release dut.reg_file_.b2v_latch_hl2_lo.db;
256
   release dut.reg_file_.b2v_latch_hl2_hi.db;
257
   // Preset ix
258
   force dut.reg_file_.b2v_latch_ix_lo.we=1;
259
   force dut.reg_file_.b2v_latch_ix_hi.we=1;
260
   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
261
   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
262
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
263
   release dut.reg_file_.b2v_latch_ix_hi.we;
264
   release dut.reg_file_.b2v_latch_ix_lo.db;
265
   release dut.reg_file_.b2v_latch_ix_hi.db;
266
   // Preset iy
267
   force dut.reg_file_.b2v_latch_iy_lo.we=1;
268
   force dut.reg_file_.b2v_latch_iy_hi.we=1;
269
   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
270
   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
271
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
272
   release dut.reg_file_.b2v_latch_iy_hi.we;
273
   release dut.reg_file_.b2v_latch_iy_lo.db;
274
   release dut.reg_file_.b2v_latch_iy_hi.db;
275
   // Preset sp
276
   force dut.reg_file_.b2v_latch_sp_lo.we=1;
277
   force dut.reg_file_.b2v_latch_sp_hi.we=1;
278
   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
279
   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
280
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
281
   release dut.reg_file_.b2v_latch_sp_hi.we;
282
   release dut.reg_file_.b2v_latch_sp_lo.db;
283
   release dut.reg_file_.b2v_latch_sp_hi.db;
284
   // Preset wz
285
   force dut.reg_file_.b2v_latch_wz_lo.we=1;
286
   force dut.reg_file_.b2v_latch_wz_hi.we=1;
287
   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
288
   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
289
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
290
   release dut.reg_file_.b2v_latch_wz_hi.we;
291
   release dut.reg_file_.b2v_latch_wz_lo.db;
292
   release dut.reg_file_.b2v_latch_wz_hi.db;
293
   // Preset pc
294
   force dut.reg_file_.b2v_latch_pc_lo.we=1;
295
   force dut.reg_file_.b2v_latch_pc_hi.we=1;
296
   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
297
   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
298
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
299
   release dut.reg_file_.b2v_latch_pc_hi.we;
300
   release dut.reg_file_.b2v_latch_pc_lo.db;
301
   release dut.reg_file_.b2v_latch_pc_hi.db;
302
   // Preset ir
303
   force dut.reg_file_.b2v_latch_ir_lo.we=1;
304
   force dut.reg_file_.b2v_latch_ir_hi.we=1;
305
   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
306
   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
307
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
308
   release dut.reg_file_.b2v_latch_ir_hi.we;
309
   release dut.reg_file_.b2v_latch_ir_lo.db;
310
   release dut.reg_file_.b2v_latch_ir_hi.db;
311
   // Preset memory
312
   ram.Mem[0] = 8'hed;
313
   ram.Mem[1] = 8'h67;
314
   // Preset memory
315
   ram.Mem[47582] = 8'h93;
316
   force dut.z80_top_ifc_n.fpga_reset=0;
317
   force dut.address_latch_.abus=16'h0000;
318
   release dut.reg_control_.ctl_reg_sys_we;
319
   release dut.reg_file_.reg_gp_we;
320
#3
321
   release dut.address_latch_.abus;
322
#1
323
#34 // Execute
324
   force dut.reg_control_.ctl_reg_sys_we=0;
325
#2 pc=z.A;
326
#2
327
#1 force dut.reg_file_.reg_gp_we=0;
328
   force dut.z80_top_ifc_n.fpga_reset=1;
329
   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h24) $fdisplay(f,"* Reg af f=%h !=24",dut.reg_file_.b2v_latch_af_lo.latch);
330
   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h33) $fdisplay(f,"* Reg af a=%h !=33",dut.reg_file_.b2v_latch_af_hi.latch);
331
   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h6a) $fdisplay(f,"* Reg bc c=%h !=6a",dut.reg_file_.b2v_latch_bc_lo.latch);
332
   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hb1) $fdisplay(f,"* Reg bc b=%h !=b1",dut.reg_file_.b2v_latch_bc_hi.latch);
333
   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hdb) $fdisplay(f,"* Reg de e=%h !=db",dut.reg_file_.b2v_latch_de_lo.latch);
334
   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'ha4) $fdisplay(f,"* Reg de d=%h !=a4",dut.reg_file_.b2v_latch_de_hi.latch);
335
   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'hde) $fdisplay(f,"* Reg hl l=%h !=de",dut.reg_file_.b2v_latch_hl_lo.latch);
336
   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hb9) $fdisplay(f,"* Reg hl h=%h !=b9",dut.reg_file_.b2v_latch_hl_hi.latch);
337
   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
338
   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
339
   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
340
   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
341
   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
342
   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
343
   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
344
   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
345
   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
346
   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
347
   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
348
   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
349
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
350
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
351
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
352
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
353
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
354
   if (ram.Mem[47582]!==8'h69) $fdisplay(f,"* Mem[b9de]=%h !=69",ram.Mem[47582]);
355
//--------------------------------------------------------------------------------
356
   force dut.instruction_reg_.ctl_ir_we=1;
357
   force dut.instruction_reg_.db=0;
358
#2 release dut.instruction_reg_.ctl_ir_we;
359
   release dut.instruction_reg_.db;
360
$fdisplay(f,"Testing opcode ed6f    RLD");
361
   // Preset af
362
   force dut.reg_file_.b2v_latch_af_lo.we=1;
363
   force dut.reg_file_.b2v_latch_af_hi.we=1;
364
   force dut.reg_file_.b2v_latch_af_lo.db=8'h8b;
365
   force dut.reg_file_.b2v_latch_af_hi.db=8'h65;
366
#2 release dut.reg_file_.b2v_latch_af_lo.we;
367
   release dut.reg_file_.b2v_latch_af_hi.we;
368
   release dut.reg_file_.b2v_latch_af_lo.db;
369
   release dut.reg_file_.b2v_latch_af_hi.db;
370
   // Preset bc
371
   force dut.reg_file_.b2v_latch_bc_lo.we=1;
372
   force dut.reg_file_.b2v_latch_bc_hi.we=1;
373
   force dut.reg_file_.b2v_latch_bc_lo.db=8'h7a;
374
   force dut.reg_file_.b2v_latch_bc_hi.db=8'h7a;
375
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
376
   release dut.reg_file_.b2v_latch_bc_hi.we;
377
   release dut.reg_file_.b2v_latch_bc_lo.db;
378
   release dut.reg_file_.b2v_latch_bc_hi.db;
379
   // Preset de
380
   force dut.reg_file_.b2v_latch_de_lo.we=1;
381
   force dut.reg_file_.b2v_latch_de_hi.we=1;
382
   force dut.reg_file_.b2v_latch_de_lo.db=8'hf0;
383
   force dut.reg_file_.b2v_latch_de_hi.db=8'hec;
384
#2 release dut.reg_file_.b2v_latch_de_lo.we;
385
   release dut.reg_file_.b2v_latch_de_hi.we;
386
   release dut.reg_file_.b2v_latch_de_lo.db;
387
   release dut.reg_file_.b2v_latch_de_hi.db;
388
   // Preset hl
389
   force dut.reg_file_.b2v_latch_hl_lo.we=1;
390
   force dut.reg_file_.b2v_latch_hl_hi.we=1;
391
   force dut.reg_file_.b2v_latch_hl_lo.db=8'h3c;
392
   force dut.reg_file_.b2v_latch_hl_hi.db=8'h40;
393
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
394
   release dut.reg_file_.b2v_latch_hl_hi.we;
395
   release dut.reg_file_.b2v_latch_hl_lo.db;
396
   release dut.reg_file_.b2v_latch_hl_hi.db;
397
   // Preset af2
398
   force dut.reg_file_.b2v_latch_af2_lo.we=1;
399
   force dut.reg_file_.b2v_latch_af2_hi.we=1;
400
   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
401
   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
402
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
403
   release dut.reg_file_.b2v_latch_af2_hi.we;
404
   release dut.reg_file_.b2v_latch_af2_lo.db;
405
   release dut.reg_file_.b2v_latch_af2_hi.db;
406
   // Preset bc2
407
   force dut.reg_file_.b2v_latch_bc2_lo.we=1;
408
   force dut.reg_file_.b2v_latch_bc2_hi.we=1;
409
   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
410
   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
411
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
412
   release dut.reg_file_.b2v_latch_bc2_hi.we;
413
   release dut.reg_file_.b2v_latch_bc2_lo.db;
414
   release dut.reg_file_.b2v_latch_bc2_hi.db;
415
   // Preset de2
416
   force dut.reg_file_.b2v_latch_de2_lo.we=1;
417
   force dut.reg_file_.b2v_latch_de2_hi.we=1;
418
   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
419
   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
420
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
421
   release dut.reg_file_.b2v_latch_de2_hi.we;
422
   release dut.reg_file_.b2v_latch_de2_lo.db;
423
   release dut.reg_file_.b2v_latch_de2_hi.db;
424
   // Preset hl2
425
   force dut.reg_file_.b2v_latch_hl2_lo.we=1;
426
   force dut.reg_file_.b2v_latch_hl2_hi.we=1;
427
   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
428
   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
429
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
430
   release dut.reg_file_.b2v_latch_hl2_hi.we;
431
   release dut.reg_file_.b2v_latch_hl2_lo.db;
432
   release dut.reg_file_.b2v_latch_hl2_hi.db;
433
   // Preset ix
434
   force dut.reg_file_.b2v_latch_ix_lo.we=1;
435
   force dut.reg_file_.b2v_latch_ix_hi.we=1;
436
   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
437
   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
438
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
439
   release dut.reg_file_.b2v_latch_ix_hi.we;
440
   release dut.reg_file_.b2v_latch_ix_lo.db;
441
   release dut.reg_file_.b2v_latch_ix_hi.db;
442
   // Preset iy
443
   force dut.reg_file_.b2v_latch_iy_lo.we=1;
444
   force dut.reg_file_.b2v_latch_iy_hi.we=1;
445
   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
446
   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
447
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
448
   release dut.reg_file_.b2v_latch_iy_hi.we;
449
   release dut.reg_file_.b2v_latch_iy_lo.db;
450
   release dut.reg_file_.b2v_latch_iy_hi.db;
451
   // Preset sp
452
   force dut.reg_file_.b2v_latch_sp_lo.we=1;
453
   force dut.reg_file_.b2v_latch_sp_hi.we=1;
454
   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
455
   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
456
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
457
   release dut.reg_file_.b2v_latch_sp_hi.we;
458
   release dut.reg_file_.b2v_latch_sp_lo.db;
459
   release dut.reg_file_.b2v_latch_sp_hi.db;
460
   // Preset wz
461
   force dut.reg_file_.b2v_latch_wz_lo.we=1;
462
   force dut.reg_file_.b2v_latch_wz_hi.we=1;
463
   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
464
   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
465
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
466
   release dut.reg_file_.b2v_latch_wz_hi.we;
467
   release dut.reg_file_.b2v_latch_wz_lo.db;
468
   release dut.reg_file_.b2v_latch_wz_hi.db;
469
   // Preset pc
470
   force dut.reg_file_.b2v_latch_pc_lo.we=1;
471
   force dut.reg_file_.b2v_latch_pc_hi.we=1;
472
   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
473
   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
474
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
475
   release dut.reg_file_.b2v_latch_pc_hi.we;
476
   release dut.reg_file_.b2v_latch_pc_lo.db;
477
   release dut.reg_file_.b2v_latch_pc_hi.db;
478
   // Preset ir
479
   force dut.reg_file_.b2v_latch_ir_lo.we=1;
480
   force dut.reg_file_.b2v_latch_ir_hi.we=1;
481
   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
482
   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
483
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
484
   release dut.reg_file_.b2v_latch_ir_hi.we;
485
   release dut.reg_file_.b2v_latch_ir_lo.db;
486
   release dut.reg_file_.b2v_latch_ir_hi.db;
487
   // Preset memory
488
   ram.Mem[0] = 8'hed;
489
   ram.Mem[1] = 8'h6f;
490
   // Preset memory
491
   ram.Mem[16444] = 8'hc4;
492
   force dut.z80_top_ifc_n.fpga_reset=0;
493
   force dut.address_latch_.abus=16'h0000;
494
   release dut.reg_control_.ctl_reg_sys_we;
495
   release dut.reg_file_.reg_gp_we;
496
#3
497
   release dut.address_latch_.abus;
498
#1
499
#34 // Execute
500
   force dut.reg_control_.ctl_reg_sys_we=0;
501
#2 pc=z.A;
502
#2
503
#1 force dut.reg_file_.reg_gp_we=0;
504
   force dut.z80_top_ifc_n.fpga_reset=1;
505
   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h2d) $fdisplay(f,"* Reg af f=%h !=2d",dut.reg_file_.b2v_latch_af_lo.latch);
506
   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h6c) $fdisplay(f,"* Reg af a=%h !=6c",dut.reg_file_.b2v_latch_af_hi.latch);
507
   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h7a) $fdisplay(f,"* Reg bc c=%h !=7a",dut.reg_file_.b2v_latch_bc_lo.latch);
508
   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h7a) $fdisplay(f,"* Reg bc b=%h !=7a",dut.reg_file_.b2v_latch_bc_hi.latch);
509
   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hf0) $fdisplay(f,"* Reg de e=%h !=f0",dut.reg_file_.b2v_latch_de_lo.latch);
510
   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hec) $fdisplay(f,"* Reg de d=%h !=ec",dut.reg_file_.b2v_latch_de_hi.latch);
511
   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h3c) $fdisplay(f,"* Reg hl l=%h !=3c",dut.reg_file_.b2v_latch_hl_lo.latch);
512
   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h40) $fdisplay(f,"* Reg hl h=%h !=40",dut.reg_file_.b2v_latch_hl_hi.latch);
513
   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
514
   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
515
   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
516
   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
517
   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
518
   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
519
   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
520
   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
521
   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
522
   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
523
   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
524
   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
525
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
526
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
527
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
528
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
529
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
530
   if (ram.Mem[16444]!==8'h45) $fdisplay(f,"* Mem[403c]=%h !=45",ram.Mem[16444]);
531
//--------------------------------------------------------------------------------
532
   force dut.instruction_reg_.ctl_ir_we=1;
533
   force dut.instruction_reg_.db=0;
534
#2 release dut.instruction_reg_.ctl_ir_we;
535
   release dut.instruction_reg_.db;
536
$fdisplay(f,"Testing opcode 81      ADD A,C");
537
   // Preset af
538
   force dut.reg_file_.b2v_latch_af_lo.we=1;
539
   force dut.reg_file_.b2v_latch_af_hi.we=1;
540
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
541
   force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
542
#2 release dut.reg_file_.b2v_latch_af_lo.we;
543
   release dut.reg_file_.b2v_latch_af_hi.we;
544
   release dut.reg_file_.b2v_latch_af_lo.db;
545
   release dut.reg_file_.b2v_latch_af_hi.db;
546
   // Preset bc
547
   force dut.reg_file_.b2v_latch_bc_lo.we=1;
548
   force dut.reg_file_.b2v_latch_bc_hi.we=1;
549
   force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
550
   force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
551
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
552
   release dut.reg_file_.b2v_latch_bc_hi.we;
553
   release dut.reg_file_.b2v_latch_bc_lo.db;
554
   release dut.reg_file_.b2v_latch_bc_hi.db;
555
   // Preset de
556
   force dut.reg_file_.b2v_latch_de_lo.we=1;
557
   force dut.reg_file_.b2v_latch_de_hi.we=1;
558
   force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
559
   force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
560
#2 release dut.reg_file_.b2v_latch_de_lo.we;
561
   release dut.reg_file_.b2v_latch_de_hi.we;
562
   release dut.reg_file_.b2v_latch_de_lo.db;
563
   release dut.reg_file_.b2v_latch_de_hi.db;
564
   // Preset hl
565
   force dut.reg_file_.b2v_latch_hl_lo.we=1;
566
   force dut.reg_file_.b2v_latch_hl_hi.we=1;
567
   force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
568
   force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
569
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
570
   release dut.reg_file_.b2v_latch_hl_hi.we;
571
   release dut.reg_file_.b2v_latch_hl_lo.db;
572
   release dut.reg_file_.b2v_latch_hl_hi.db;
573
   // Preset af2
574
   force dut.reg_file_.b2v_latch_af2_lo.we=1;
575
   force dut.reg_file_.b2v_latch_af2_hi.we=1;
576
   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
577
   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
578
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
579
   release dut.reg_file_.b2v_latch_af2_hi.we;
580
   release dut.reg_file_.b2v_latch_af2_lo.db;
581
   release dut.reg_file_.b2v_latch_af2_hi.db;
582
   // Preset bc2
583
   force dut.reg_file_.b2v_latch_bc2_lo.we=1;
584
   force dut.reg_file_.b2v_latch_bc2_hi.we=1;
585
   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
586
   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
587
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
588
   release dut.reg_file_.b2v_latch_bc2_hi.we;
589
   release dut.reg_file_.b2v_latch_bc2_lo.db;
590
   release dut.reg_file_.b2v_latch_bc2_hi.db;
591
   // Preset de2
592
   force dut.reg_file_.b2v_latch_de2_lo.we=1;
593
   force dut.reg_file_.b2v_latch_de2_hi.we=1;
594
   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
595
   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
596
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
597
   release dut.reg_file_.b2v_latch_de2_hi.we;
598
   release dut.reg_file_.b2v_latch_de2_lo.db;
599
   release dut.reg_file_.b2v_latch_de2_hi.db;
600
   // Preset hl2
601
   force dut.reg_file_.b2v_latch_hl2_lo.we=1;
602
   force dut.reg_file_.b2v_latch_hl2_hi.we=1;
603
   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
604
   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
605
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
606
   release dut.reg_file_.b2v_latch_hl2_hi.we;
607
   release dut.reg_file_.b2v_latch_hl2_lo.db;
608
   release dut.reg_file_.b2v_latch_hl2_hi.db;
609
   // Preset ix
610
   force dut.reg_file_.b2v_latch_ix_lo.we=1;
611
   force dut.reg_file_.b2v_latch_ix_hi.we=1;
612
   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
613
   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
614
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
615
   release dut.reg_file_.b2v_latch_ix_hi.we;
616
   release dut.reg_file_.b2v_latch_ix_lo.db;
617
   release dut.reg_file_.b2v_latch_ix_hi.db;
618
   // Preset iy
619
   force dut.reg_file_.b2v_latch_iy_lo.we=1;
620
   force dut.reg_file_.b2v_latch_iy_hi.we=1;
621
   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
622
   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
623
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
624
   release dut.reg_file_.b2v_latch_iy_hi.we;
625
   release dut.reg_file_.b2v_latch_iy_lo.db;
626
   release dut.reg_file_.b2v_latch_iy_hi.db;
627
   // Preset sp
628
   force dut.reg_file_.b2v_latch_sp_lo.we=1;
629
   force dut.reg_file_.b2v_latch_sp_hi.we=1;
630
   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
631
   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
632
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
633
   release dut.reg_file_.b2v_latch_sp_hi.we;
634
   release dut.reg_file_.b2v_latch_sp_lo.db;
635
   release dut.reg_file_.b2v_latch_sp_hi.db;
636
   // Preset wz
637
   force dut.reg_file_.b2v_latch_wz_lo.we=1;
638
   force dut.reg_file_.b2v_latch_wz_hi.we=1;
639
   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
640
   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
641
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
642
   release dut.reg_file_.b2v_latch_wz_hi.we;
643
   release dut.reg_file_.b2v_latch_wz_lo.db;
644
   release dut.reg_file_.b2v_latch_wz_hi.db;
645
   // Preset pc
646
   force dut.reg_file_.b2v_latch_pc_lo.we=1;
647
   force dut.reg_file_.b2v_latch_pc_hi.we=1;
648
   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
649
   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
650
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
651
   release dut.reg_file_.b2v_latch_pc_hi.we;
652
   release dut.reg_file_.b2v_latch_pc_lo.db;
653
   release dut.reg_file_.b2v_latch_pc_hi.db;
654
   // Preset ir
655
   force dut.reg_file_.b2v_latch_ir_lo.we=1;
656
   force dut.reg_file_.b2v_latch_ir_hi.we=1;
657
   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
658
   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
659
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
660
   release dut.reg_file_.b2v_latch_ir_hi.we;
661
   release dut.reg_file_.b2v_latch_ir_lo.db;
662
   release dut.reg_file_.b2v_latch_ir_hi.db;
663
   // Preset memory
664
   ram.Mem[0] = 8'h81;
665
   // Preset memory
666
   ram.Mem[56486] = 8'h49;
667
   force dut.z80_top_ifc_n.fpga_reset=0;
668
   force dut.address_latch_.abus=16'h0000;
669
   release dut.reg_control_.ctl_reg_sys_we;
670
   release dut.reg_file_.reg_gp_we;
671
#3
672
   release dut.address_latch_.abus;
673
#1
674
#6 // Execute
675
   force dut.reg_control_.ctl_reg_sys_we=0;
676
#2 pc=z.A;
677
#2
678
#1 force dut.reg_file_.reg_gp_we=0;
679
   force dut.z80_top_ifc_n.fpga_reset=1;
680
   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h31) $fdisplay(f,"* Reg af f=%h !=31",dut.reg_file_.b2v_latch_af_lo.latch);
681
   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h30) $fdisplay(f,"* Reg af a=%h !=30",dut.reg_file_.b2v_latch_af_hi.latch);
682
   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
683
   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
684
   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
685
   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
686
   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
687
   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
688
   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
689
   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
690
   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
691
   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
692
   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
693
   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
694
   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
695
   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
696
   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
697
   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
698
   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
699
   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
700
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
701
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
702
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
703
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
704
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
705
//--------------------------------------------------------------------------------
706
   force dut.instruction_reg_.ctl_ir_we=1;
707
   force dut.instruction_reg_.db=0;
708
#2 release dut.instruction_reg_.ctl_ir_we;
709
   release dut.instruction_reg_.db;
710
$fdisplay(f,"Testing opcode cb41    BIT 0,C");
711
   // Preset af
712
   force dut.reg_file_.b2v_latch_af_lo.we=1;
713
   force dut.reg_file_.b2v_latch_af_hi.we=1;
714
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
715
   force dut.reg_file_.b2v_latch_af_hi.db=8'h9e;
716
#2 release dut.reg_file_.b2v_latch_af_lo.we;
717
   release dut.reg_file_.b2v_latch_af_hi.we;
718
   release dut.reg_file_.b2v_latch_af_lo.db;
719
   release dut.reg_file_.b2v_latch_af_hi.db;
720
   // Preset bc
721
   force dut.reg_file_.b2v_latch_bc_lo.we=1;
722
   force dut.reg_file_.b2v_latch_bc_hi.we=1;
723
   force dut.reg_file_.b2v_latch_bc_lo.db=8'h43;
724
   force dut.reg_file_.b2v_latch_bc_hi.db=8'h1b;
725
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
726
   release dut.reg_file_.b2v_latch_bc_hi.we;
727
   release dut.reg_file_.b2v_latch_bc_lo.db;
728
   release dut.reg_file_.b2v_latch_bc_hi.db;
729
   // Preset de
730
   force dut.reg_file_.b2v_latch_de_lo.we=1;
731
   force dut.reg_file_.b2v_latch_de_hi.we=1;
732
   force dut.reg_file_.b2v_latch_de_lo.db=8'h4e;
733
   force dut.reg_file_.b2v_latch_de_hi.db=8'h95;
734
#2 release dut.reg_file_.b2v_latch_de_lo.we;
735
   release dut.reg_file_.b2v_latch_de_hi.we;
736
   release dut.reg_file_.b2v_latch_de_lo.db;
737
   release dut.reg_file_.b2v_latch_de_hi.db;
738
   // Preset hl
739
   force dut.reg_file_.b2v_latch_hl_lo.we=1;
740
   force dut.reg_file_.b2v_latch_hl_hi.we=1;
741
   force dut.reg_file_.b2v_latch_hl_lo.db=8'he9;
742
   force dut.reg_file_.b2v_latch_hl_hi.db=8'h7b;
743
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
744
   release dut.reg_file_.b2v_latch_hl_hi.we;
745
   release dut.reg_file_.b2v_latch_hl_lo.db;
746
   release dut.reg_file_.b2v_latch_hl_hi.db;
747
   // Preset af2
748
   force dut.reg_file_.b2v_latch_af2_lo.we=1;
749
   force dut.reg_file_.b2v_latch_af2_hi.we=1;
750
   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
751
   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
752
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
753
   release dut.reg_file_.b2v_latch_af2_hi.we;
754
   release dut.reg_file_.b2v_latch_af2_lo.db;
755
   release dut.reg_file_.b2v_latch_af2_hi.db;
756
   // Preset bc2
757
   force dut.reg_file_.b2v_latch_bc2_lo.we=1;
758
   force dut.reg_file_.b2v_latch_bc2_hi.we=1;
759
   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
760
   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
761
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
762
   release dut.reg_file_.b2v_latch_bc2_hi.we;
763
   release dut.reg_file_.b2v_latch_bc2_lo.db;
764
   release dut.reg_file_.b2v_latch_bc2_hi.db;
765
   // Preset de2
766
   force dut.reg_file_.b2v_latch_de2_lo.we=1;
767
   force dut.reg_file_.b2v_latch_de2_hi.we=1;
768
   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
769
   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
770
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
771
   release dut.reg_file_.b2v_latch_de2_hi.we;
772
   release dut.reg_file_.b2v_latch_de2_lo.db;
773
   release dut.reg_file_.b2v_latch_de2_hi.db;
774
   // Preset hl2
775
   force dut.reg_file_.b2v_latch_hl2_lo.we=1;
776
   force dut.reg_file_.b2v_latch_hl2_hi.we=1;
777
   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
778
   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
779
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
780
   release dut.reg_file_.b2v_latch_hl2_hi.we;
781
   release dut.reg_file_.b2v_latch_hl2_lo.db;
782
   release dut.reg_file_.b2v_latch_hl2_hi.db;
783
   // Preset ix
784
   force dut.reg_file_.b2v_latch_ix_lo.we=1;
785
   force dut.reg_file_.b2v_latch_ix_hi.we=1;
786
   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
787
   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
788
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
789
   release dut.reg_file_.b2v_latch_ix_hi.we;
790
   release dut.reg_file_.b2v_latch_ix_lo.db;
791
   release dut.reg_file_.b2v_latch_ix_hi.db;
792
   // Preset iy
793
   force dut.reg_file_.b2v_latch_iy_lo.we=1;
794
   force dut.reg_file_.b2v_latch_iy_hi.we=1;
795
   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
796
   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
797
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
798
   release dut.reg_file_.b2v_latch_iy_hi.we;
799
   release dut.reg_file_.b2v_latch_iy_lo.db;
800
   release dut.reg_file_.b2v_latch_iy_hi.db;
801
   // Preset sp
802
   force dut.reg_file_.b2v_latch_sp_lo.we=1;
803
   force dut.reg_file_.b2v_latch_sp_hi.we=1;
804
   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
805
   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
806
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
807
   release dut.reg_file_.b2v_latch_sp_hi.we;
808
   release dut.reg_file_.b2v_latch_sp_lo.db;
809
   release dut.reg_file_.b2v_latch_sp_hi.db;
810
   // Preset wz
811
   force dut.reg_file_.b2v_latch_wz_lo.we=1;
812
   force dut.reg_file_.b2v_latch_wz_hi.we=1;
813
   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
814
   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
815
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
816
   release dut.reg_file_.b2v_latch_wz_hi.we;
817
   release dut.reg_file_.b2v_latch_wz_lo.db;
818
   release dut.reg_file_.b2v_latch_wz_hi.db;
819
   // Preset pc
820
   force dut.reg_file_.b2v_latch_pc_lo.we=1;
821
   force dut.reg_file_.b2v_latch_pc_hi.we=1;
822
   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
823
   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
824
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
825
   release dut.reg_file_.b2v_latch_pc_hi.we;
826
   release dut.reg_file_.b2v_latch_pc_lo.db;
827
   release dut.reg_file_.b2v_latch_pc_hi.db;
828
   // Preset ir
829
   force dut.reg_file_.b2v_latch_ir_lo.we=1;
830
   force dut.reg_file_.b2v_latch_ir_hi.we=1;
831
   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
832
   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
833
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
834
   release dut.reg_file_.b2v_latch_ir_hi.we;
835
   release dut.reg_file_.b2v_latch_ir_lo.db;
836
   release dut.reg_file_.b2v_latch_ir_hi.db;
837
   // Preset memory
838
   ram.Mem[0] = 8'hcb;
839
   ram.Mem[1] = 8'h41;
840
   // Preset memory
841
   ram.Mem[31721] = 8'hf7;
842
   force dut.z80_top_ifc_n.fpga_reset=0;
843
   force dut.address_latch_.abus=16'h0000;
844
   release dut.reg_control_.ctl_reg_sys_we;
845
   release dut.reg_file_.reg_gp_we;
846
#3
847
   release dut.address_latch_.abus;
848
#1
849
#14 // Execute
850
   force dut.reg_control_.ctl_reg_sys_we=0;
851
#2 pc=z.A;
852
#2
853
#1 force dut.reg_file_.reg_gp_we=0;
854
   force dut.z80_top_ifc_n.fpga_reset=1;
855
   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h10) $fdisplay(f,"* Reg af f=%h !=10",dut.reg_file_.b2v_latch_af_lo.latch);
856
   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h9e) $fdisplay(f,"* Reg af a=%h !=9e",dut.reg_file_.b2v_latch_af_hi.latch);
857
   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h43) $fdisplay(f,"* Reg bc c=%h !=43",dut.reg_file_.b2v_latch_bc_lo.latch);
858
   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h1b) $fdisplay(f,"* Reg bc b=%h !=1b",dut.reg_file_.b2v_latch_bc_hi.latch);
859
   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h4e) $fdisplay(f,"* Reg de e=%h !=4e",dut.reg_file_.b2v_latch_de_lo.latch);
860
   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h95) $fdisplay(f,"* Reg de d=%h !=95",dut.reg_file_.b2v_latch_de_hi.latch);
861
   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'he9) $fdisplay(f,"* Reg hl l=%h !=e9",dut.reg_file_.b2v_latch_hl_lo.latch);
862
   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h7b) $fdisplay(f,"* Reg hl h=%h !=7b",dut.reg_file_.b2v_latch_hl_hi.latch);
863
   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
864
   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
865
   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
866
   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
867
   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
868
   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
869
   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
870
   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
871
   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
872
   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
873
   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
874
   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
875
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
876
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
877
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
878
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
879
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
880
//--------------------------------------------------------------------------------
881
   force dut.instruction_reg_.ctl_ir_we=1;
882
   force dut.instruction_reg_.db=0;
883
#2 release dut.instruction_reg_.ctl_ir_we;
884
   release dut.instruction_reg_.db;
885
$fdisplay(f,"Testing opcode cb93    RES 2,E");
886
   // Preset af
887
   force dut.reg_file_.b2v_latch_af_lo.we=1;
888
   force dut.reg_file_.b2v_latch_af_hi.we=1;
889
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
890
   force dut.reg_file_.b2v_latch_af_hi.db=8'hc2;
891
#2 release dut.reg_file_.b2v_latch_af_lo.we;
892
   release dut.reg_file_.b2v_latch_af_hi.we;
893
   release dut.reg_file_.b2v_latch_af_lo.db;
894
   release dut.reg_file_.b2v_latch_af_hi.db;
895
   // Preset bc
896
   force dut.reg_file_.b2v_latch_bc_lo.we=1;
897
   force dut.reg_file_.b2v_latch_bc_hi.we=1;
898
   force dut.reg_file_.b2v_latch_bc_lo.db=8'h05;
899
   force dut.reg_file_.b2v_latch_bc_hi.db=8'h4e;
900
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
901
   release dut.reg_file_.b2v_latch_bc_hi.we;
902
   release dut.reg_file_.b2v_latch_bc_lo.db;
903
   release dut.reg_file_.b2v_latch_bc_hi.db;
904
   // Preset de
905
   force dut.reg_file_.b2v_latch_de_lo.we=1;
906
   force dut.reg_file_.b2v_latch_de_hi.we=1;
907
   force dut.reg_file_.b2v_latch_de_lo.db=8'hf8;
908
   force dut.reg_file_.b2v_latch_de_hi.db=8'hb3;
909
#2 release dut.reg_file_.b2v_latch_de_lo.we;
910
   release dut.reg_file_.b2v_latch_de_hi.we;
911
   release dut.reg_file_.b2v_latch_de_lo.db;
912
   release dut.reg_file_.b2v_latch_de_hi.db;
913
   // Preset hl
914
   force dut.reg_file_.b2v_latch_hl_lo.we=1;
915
   force dut.reg_file_.b2v_latch_hl_hi.we=1;
916
   force dut.reg_file_.b2v_latch_hl_lo.db=8'h34;
917
   force dut.reg_file_.b2v_latch_hl_hi.db=8'h22;
918
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
919
   release dut.reg_file_.b2v_latch_hl_hi.we;
920
   release dut.reg_file_.b2v_latch_hl_lo.db;
921
   release dut.reg_file_.b2v_latch_hl_hi.db;
922
   // Preset af2
923
   force dut.reg_file_.b2v_latch_af2_lo.we=1;
924
   force dut.reg_file_.b2v_latch_af2_hi.we=1;
925
   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
926
   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
927
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
928
   release dut.reg_file_.b2v_latch_af2_hi.we;
929
   release dut.reg_file_.b2v_latch_af2_lo.db;
930
   release dut.reg_file_.b2v_latch_af2_hi.db;
931
   // Preset bc2
932
   force dut.reg_file_.b2v_latch_bc2_lo.we=1;
933
   force dut.reg_file_.b2v_latch_bc2_hi.we=1;
934
   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
935
   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
936
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
937
   release dut.reg_file_.b2v_latch_bc2_hi.we;
938
   release dut.reg_file_.b2v_latch_bc2_lo.db;
939
   release dut.reg_file_.b2v_latch_bc2_hi.db;
940
   // Preset de2
941
   force dut.reg_file_.b2v_latch_de2_lo.we=1;
942
   force dut.reg_file_.b2v_latch_de2_hi.we=1;
943
   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
944
   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
945
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
946
   release dut.reg_file_.b2v_latch_de2_hi.we;
947
   release dut.reg_file_.b2v_latch_de2_lo.db;
948
   release dut.reg_file_.b2v_latch_de2_hi.db;
949
   // Preset hl2
950
   force dut.reg_file_.b2v_latch_hl2_lo.we=1;
951
   force dut.reg_file_.b2v_latch_hl2_hi.we=1;
952
   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
953
   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
954
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
955
   release dut.reg_file_.b2v_latch_hl2_hi.we;
956
   release dut.reg_file_.b2v_latch_hl2_lo.db;
957
   release dut.reg_file_.b2v_latch_hl2_hi.db;
958
   // Preset ix
959
   force dut.reg_file_.b2v_latch_ix_lo.we=1;
960
   force dut.reg_file_.b2v_latch_ix_hi.we=1;
961
   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
962
   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
963
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
964
   release dut.reg_file_.b2v_latch_ix_hi.we;
965
   release dut.reg_file_.b2v_latch_ix_lo.db;
966
   release dut.reg_file_.b2v_latch_ix_hi.db;
967
   // Preset iy
968
   force dut.reg_file_.b2v_latch_iy_lo.we=1;
969
   force dut.reg_file_.b2v_latch_iy_hi.we=1;
970
   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
971
   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
972
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
973
   release dut.reg_file_.b2v_latch_iy_hi.we;
974
   release dut.reg_file_.b2v_latch_iy_lo.db;
975
   release dut.reg_file_.b2v_latch_iy_hi.db;
976
   // Preset sp
977
   force dut.reg_file_.b2v_latch_sp_lo.we=1;
978
   force dut.reg_file_.b2v_latch_sp_hi.we=1;
979
   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
980
   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
981
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
982
   release dut.reg_file_.b2v_latch_sp_hi.we;
983
   release dut.reg_file_.b2v_latch_sp_lo.db;
984
   release dut.reg_file_.b2v_latch_sp_hi.db;
985
   // Preset wz
986
   force dut.reg_file_.b2v_latch_wz_lo.we=1;
987
   force dut.reg_file_.b2v_latch_wz_hi.we=1;
988
   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
989
   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
990
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
991
   release dut.reg_file_.b2v_latch_wz_hi.we;
992
   release dut.reg_file_.b2v_latch_wz_lo.db;
993
   release dut.reg_file_.b2v_latch_wz_hi.db;
994
   // Preset pc
995
   force dut.reg_file_.b2v_latch_pc_lo.we=1;
996
   force dut.reg_file_.b2v_latch_pc_hi.we=1;
997
   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
998
   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
999
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
1000
   release dut.reg_file_.b2v_latch_pc_hi.we;
1001
   release dut.reg_file_.b2v_latch_pc_lo.db;
1002
   release dut.reg_file_.b2v_latch_pc_hi.db;
1003
   // Preset ir
1004
   force dut.reg_file_.b2v_latch_ir_lo.we=1;
1005
   force dut.reg_file_.b2v_latch_ir_hi.we=1;
1006
   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
1007
   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
1008
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
1009
   release dut.reg_file_.b2v_latch_ir_hi.we;
1010
   release dut.reg_file_.b2v_latch_ir_lo.db;
1011
   release dut.reg_file_.b2v_latch_ir_hi.db;
1012
   // Preset memory
1013
   ram.Mem[0] = 8'hcb;
1014
   ram.Mem[1] = 8'h93;
1015
   // Preset memory
1016
   ram.Mem[8756] = 8'ha0;
1017
   force dut.z80_top_ifc_n.fpga_reset=0;
1018
   force dut.address_latch_.abus=16'h0000;
1019
   release dut.reg_control_.ctl_reg_sys_we;
1020
   release dut.reg_file_.reg_gp_we;
1021
#3
1022
   release dut.address_latch_.abus;
1023
#1
1024
#14 // Execute
1025
   force dut.reg_control_.ctl_reg_sys_we=0;
1026
#2 pc=z.A;
1027
#2
1028
#1 force dut.reg_file_.reg_gp_we=0;
1029
   force dut.z80_top_ifc_n.fpga_reset=1;
1030
   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch);
1031
   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hc2) $fdisplay(f,"* Reg af a=%h !=c2",dut.reg_file_.b2v_latch_af_hi.latch);
1032
   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h05) $fdisplay(f,"* Reg bc c=%h !=05",dut.reg_file_.b2v_latch_bc_lo.latch);
1033
   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h4e) $fdisplay(f,"* Reg bc b=%h !=4e",dut.reg_file_.b2v_latch_bc_hi.latch);
1034
   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hf8) $fdisplay(f,"* Reg de e=%h !=f8",dut.reg_file_.b2v_latch_de_lo.latch);
1035
   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hb3) $fdisplay(f,"* Reg de d=%h !=b3",dut.reg_file_.b2v_latch_de_hi.latch);
1036
   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h34) $fdisplay(f,"* Reg hl l=%h !=34",dut.reg_file_.b2v_latch_hl_lo.latch);
1037
   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h22) $fdisplay(f,"* Reg hl h=%h !=22",dut.reg_file_.b2v_latch_hl_hi.latch);
1038
   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
1039
   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
1040
   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
1041
   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
1042
   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
1043
   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
1044
   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
1045
   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
1046
   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
1047
   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
1048
   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
1049
   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
1050
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
1051
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
1052
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
1053
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
1054
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
1055
//--------------------------------------------------------------------------------
1056
   force dut.instruction_reg_.ctl_ir_we=1;
1057
   force dut.instruction_reg_.db=0;
1058
#2 release dut.instruction_reg_.ctl_ir_we;
1059
   release dut.instruction_reg_.db;
1060
$fdisplay(f,"Testing opcode cbe5    SET 4,L");
1061
   // Preset af
1062
   force dut.reg_file_.b2v_latch_af_lo.we=1;
1063
   force dut.reg_file_.b2v_latch_af_hi.we=1;
1064
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
1065
   force dut.reg_file_.b2v_latch_af_hi.db=8'hca;
1066
#2 release dut.reg_file_.b2v_latch_af_lo.we;
1067
   release dut.reg_file_.b2v_latch_af_hi.we;
1068
   release dut.reg_file_.b2v_latch_af_lo.db;
1069
   release dut.reg_file_.b2v_latch_af_hi.db;
1070
   // Preset bc
1071
   force dut.reg_file_.b2v_latch_bc_lo.we=1;
1072
   force dut.reg_file_.b2v_latch_bc_hi.we=1;
1073
   force dut.reg_file_.b2v_latch_bc_lo.db=8'h0d;
1074
   force dut.reg_file_.b2v_latch_bc_hi.db=8'hdf;
1075
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
1076
   release dut.reg_file_.b2v_latch_bc_hi.we;
1077
   release dut.reg_file_.b2v_latch_bc_lo.db;
1078
   release dut.reg_file_.b2v_latch_bc_hi.db;
1079
   // Preset de
1080
   force dut.reg_file_.b2v_latch_de_lo.we=1;
1081
   force dut.reg_file_.b2v_latch_de_hi.we=1;
1082
   force dut.reg_file_.b2v_latch_de_lo.db=8'h88;
1083
   force dut.reg_file_.b2v_latch_de_hi.db=8'hd5;
1084
#2 release dut.reg_file_.b2v_latch_de_lo.we;
1085
   release dut.reg_file_.b2v_latch_de_hi.we;
1086
   release dut.reg_file_.b2v_latch_de_lo.db;
1087
   release dut.reg_file_.b2v_latch_de_hi.db;
1088
   // Preset hl
1089
   force dut.reg_file_.b2v_latch_hl_lo.we=1;
1090
   force dut.reg_file_.b2v_latch_hl_hi.we=1;
1091
   force dut.reg_file_.b2v_latch_hl_lo.db=8'h8f;
1092
   force dut.reg_file_.b2v_latch_hl_hi.db=8'hb4;
1093
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
1094
   release dut.reg_file_.b2v_latch_hl_hi.we;
1095
   release dut.reg_file_.b2v_latch_hl_lo.db;
1096
   release dut.reg_file_.b2v_latch_hl_hi.db;
1097
   // Preset af2
1098
   force dut.reg_file_.b2v_latch_af2_lo.we=1;
1099
   force dut.reg_file_.b2v_latch_af2_hi.we=1;
1100
   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
1101
   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
1102
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
1103
   release dut.reg_file_.b2v_latch_af2_hi.we;
1104
   release dut.reg_file_.b2v_latch_af2_lo.db;
1105
   release dut.reg_file_.b2v_latch_af2_hi.db;
1106
   // Preset bc2
1107
   force dut.reg_file_.b2v_latch_bc2_lo.we=1;
1108
   force dut.reg_file_.b2v_latch_bc2_hi.we=1;
1109
   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
1110
   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
1111
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
1112
   release dut.reg_file_.b2v_latch_bc2_hi.we;
1113
   release dut.reg_file_.b2v_latch_bc2_lo.db;
1114
   release dut.reg_file_.b2v_latch_bc2_hi.db;
1115
   // Preset de2
1116
   force dut.reg_file_.b2v_latch_de2_lo.we=1;
1117
   force dut.reg_file_.b2v_latch_de2_hi.we=1;
1118
   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
1119
   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
1120
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
1121
   release dut.reg_file_.b2v_latch_de2_hi.we;
1122
   release dut.reg_file_.b2v_latch_de2_lo.db;
1123
   release dut.reg_file_.b2v_latch_de2_hi.db;
1124
   // Preset hl2
1125
   force dut.reg_file_.b2v_latch_hl2_lo.we=1;
1126
   force dut.reg_file_.b2v_latch_hl2_hi.we=1;
1127
   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
1128
   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
1129
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
1130
   release dut.reg_file_.b2v_latch_hl2_hi.we;
1131
   release dut.reg_file_.b2v_latch_hl2_lo.db;
1132
   release dut.reg_file_.b2v_latch_hl2_hi.db;
1133
   // Preset ix
1134
   force dut.reg_file_.b2v_latch_ix_lo.we=1;
1135
   force dut.reg_file_.b2v_latch_ix_hi.we=1;
1136
   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
1137
   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
1138
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
1139
   release dut.reg_file_.b2v_latch_ix_hi.we;
1140
   release dut.reg_file_.b2v_latch_ix_lo.db;
1141
   release dut.reg_file_.b2v_latch_ix_hi.db;
1142
   // Preset iy
1143
   force dut.reg_file_.b2v_latch_iy_lo.we=1;
1144
   force dut.reg_file_.b2v_latch_iy_hi.we=1;
1145
   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
1146
   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
1147
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
1148
   release dut.reg_file_.b2v_latch_iy_hi.we;
1149
   release dut.reg_file_.b2v_latch_iy_lo.db;
1150
   release dut.reg_file_.b2v_latch_iy_hi.db;
1151
   // Preset sp
1152
   force dut.reg_file_.b2v_latch_sp_lo.we=1;
1153
   force dut.reg_file_.b2v_latch_sp_hi.we=1;
1154
   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
1155
   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
1156
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
1157
   release dut.reg_file_.b2v_latch_sp_hi.we;
1158
   release dut.reg_file_.b2v_latch_sp_lo.db;
1159
   release dut.reg_file_.b2v_latch_sp_hi.db;
1160
   // Preset wz
1161
   force dut.reg_file_.b2v_latch_wz_lo.we=1;
1162
   force dut.reg_file_.b2v_latch_wz_hi.we=1;
1163
   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
1164
   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
1165
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
1166
   release dut.reg_file_.b2v_latch_wz_hi.we;
1167
   release dut.reg_file_.b2v_latch_wz_lo.db;
1168
   release dut.reg_file_.b2v_latch_wz_hi.db;
1169
   // Preset pc
1170
   force dut.reg_file_.b2v_latch_pc_lo.we=1;
1171
   force dut.reg_file_.b2v_latch_pc_hi.we=1;
1172
   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
1173
   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
1174
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
1175
   release dut.reg_file_.b2v_latch_pc_hi.we;
1176
   release dut.reg_file_.b2v_latch_pc_lo.db;
1177
   release dut.reg_file_.b2v_latch_pc_hi.db;
1178
   // Preset ir
1179
   force dut.reg_file_.b2v_latch_ir_lo.we=1;
1180
   force dut.reg_file_.b2v_latch_ir_hi.we=1;
1181
   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
1182
   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
1183
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
1184
   release dut.reg_file_.b2v_latch_ir_hi.we;
1185
   release dut.reg_file_.b2v_latch_ir_lo.db;
1186
   release dut.reg_file_.b2v_latch_ir_hi.db;
1187
   // Preset memory
1188
   ram.Mem[0] = 8'hcb;
1189
   ram.Mem[1] = 8'he5;
1190
   // Preset memory
1191
   ram.Mem[46223] = 8'hcf;
1192
   force dut.z80_top_ifc_n.fpga_reset=0;
1193
   force dut.address_latch_.abus=16'h0000;
1194
   release dut.reg_control_.ctl_reg_sys_we;
1195
   release dut.reg_file_.reg_gp_we;
1196
#3
1197
   release dut.address_latch_.abus;
1198
#1
1199
#14 // Execute
1200
   force dut.reg_control_.ctl_reg_sys_we=0;
1201
#2 pc=z.A;
1202
#2
1203
#1 force dut.reg_file_.reg_gp_we=0;
1204
   force dut.z80_top_ifc_n.fpga_reset=1;
1205
   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch);
1206
   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hca) $fdisplay(f,"* Reg af a=%h !=ca",dut.reg_file_.b2v_latch_af_hi.latch);
1207
   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h0d) $fdisplay(f,"* Reg bc c=%h !=0d",dut.reg_file_.b2v_latch_bc_lo.latch);
1208
   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hdf) $fdisplay(f,"* Reg bc b=%h !=df",dut.reg_file_.b2v_latch_bc_hi.latch);
1209
   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h88) $fdisplay(f,"* Reg de e=%h !=88",dut.reg_file_.b2v_latch_de_lo.latch);
1210
   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hd5) $fdisplay(f,"* Reg de d=%h !=d5",dut.reg_file_.b2v_latch_de_hi.latch);
1211
   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h9f) $fdisplay(f,"* Reg hl l=%h !=9f",dut.reg_file_.b2v_latch_hl_lo.latch);
1212
   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hb4) $fdisplay(f,"* Reg hl h=%h !=b4",dut.reg_file_.b2v_latch_hl_hi.latch);
1213
   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
1214
   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
1215
   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
1216
   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
1217
   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
1218
   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
1219
   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
1220
   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
1221
   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
1222
   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
1223
   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
1224
   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
1225
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
1226
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
1227
   if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
1228
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
1229
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
1230
//--------------------------------------------------------------------------------
1231
   force dut.instruction_reg_.ctl_ir_we=1;
1232
   force dut.instruction_reg_.db=0;
1233
#2 release dut.instruction_reg_.ctl_ir_we;
1234
   release dut.instruction_reg_.db;
1235
$fdisplay(f,"Testing opcode 8c      ADC A,H");
1236
   // Preset af
1237
   force dut.reg_file_.b2v_latch_af_lo.we=1;
1238
   force dut.reg_file_.b2v_latch_af_hi.we=1;
1239
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
1240
   force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
1241
#2 release dut.reg_file_.b2v_latch_af_lo.we;
1242
   release dut.reg_file_.b2v_latch_af_hi.we;
1243
   release dut.reg_file_.b2v_latch_af_lo.db;
1244
   release dut.reg_file_.b2v_latch_af_hi.db;
1245
   // Preset bc
1246
   force dut.reg_file_.b2v_latch_bc_lo.we=1;
1247
   force dut.reg_file_.b2v_latch_bc_hi.we=1;
1248
   force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
1249
   force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
1250
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
1251
   release dut.reg_file_.b2v_latch_bc_hi.we;
1252
   release dut.reg_file_.b2v_latch_bc_lo.db;
1253
   release dut.reg_file_.b2v_latch_bc_hi.db;
1254
   // Preset de
1255
   force dut.reg_file_.b2v_latch_de_lo.we=1;
1256
   force dut.reg_file_.b2v_latch_de_hi.we=1;
1257
   force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
1258
   force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
1259
#2 release dut.reg_file_.b2v_latch_de_lo.we;
1260
   release dut.reg_file_.b2v_latch_de_hi.we;
1261
   release dut.reg_file_.b2v_latch_de_lo.db;
1262
   release dut.reg_file_.b2v_latch_de_hi.db;
1263
   // Preset hl
1264
   force dut.reg_file_.b2v_latch_hl_lo.we=1;
1265
   force dut.reg_file_.b2v_latch_hl_hi.we=1;
1266
   force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
1267
   force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
1268
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
1269
   release dut.reg_file_.b2v_latch_hl_hi.we;
1270
   release dut.reg_file_.b2v_latch_hl_lo.db;
1271
   release dut.reg_file_.b2v_latch_hl_hi.db;
1272
   // Preset af2
1273
   force dut.reg_file_.b2v_latch_af2_lo.we=1;
1274
   force dut.reg_file_.b2v_latch_af2_hi.we=1;
1275
   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
1276
   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
1277
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
1278
   release dut.reg_file_.b2v_latch_af2_hi.we;
1279
   release dut.reg_file_.b2v_latch_af2_lo.db;
1280
   release dut.reg_file_.b2v_latch_af2_hi.db;
1281
   // Preset bc2
1282
   force dut.reg_file_.b2v_latch_bc2_lo.we=1;
1283
   force dut.reg_file_.b2v_latch_bc2_hi.we=1;
1284
   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
1285
   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
1286
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
1287
   release dut.reg_file_.b2v_latch_bc2_hi.we;
1288
   release dut.reg_file_.b2v_latch_bc2_lo.db;
1289
   release dut.reg_file_.b2v_latch_bc2_hi.db;
1290
   // Preset de2
1291
   force dut.reg_file_.b2v_latch_de2_lo.we=1;
1292
   force dut.reg_file_.b2v_latch_de2_hi.we=1;
1293
   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
1294
   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
1295
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
1296
   release dut.reg_file_.b2v_latch_de2_hi.we;
1297
   release dut.reg_file_.b2v_latch_de2_lo.db;
1298
   release dut.reg_file_.b2v_latch_de2_hi.db;
1299
   // Preset hl2
1300
   force dut.reg_file_.b2v_latch_hl2_lo.we=1;
1301
   force dut.reg_file_.b2v_latch_hl2_hi.we=1;
1302
   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
1303
   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
1304
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
1305
   release dut.reg_file_.b2v_latch_hl2_hi.we;
1306
   release dut.reg_file_.b2v_latch_hl2_lo.db;
1307
   release dut.reg_file_.b2v_latch_hl2_hi.db;
1308
   // Preset ix
1309
   force dut.reg_file_.b2v_latch_ix_lo.we=1;
1310
   force dut.reg_file_.b2v_latch_ix_hi.we=1;
1311
   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
1312
   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
1313
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
1314
   release dut.reg_file_.b2v_latch_ix_hi.we;
1315
   release dut.reg_file_.b2v_latch_ix_lo.db;
1316
   release dut.reg_file_.b2v_latch_ix_hi.db;
1317
   // Preset iy
1318
   force dut.reg_file_.b2v_latch_iy_lo.we=1;
1319
   force dut.reg_file_.b2v_latch_iy_hi.we=1;
1320
   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
1321
   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
1322
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
1323
   release dut.reg_file_.b2v_latch_iy_hi.we;
1324
   release dut.reg_file_.b2v_latch_iy_lo.db;
1325
   release dut.reg_file_.b2v_latch_iy_hi.db;
1326
   // Preset sp
1327
   force dut.reg_file_.b2v_latch_sp_lo.we=1;
1328
   force dut.reg_file_.b2v_latch_sp_hi.we=1;
1329
   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
1330
   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
1331
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
1332
   release dut.reg_file_.b2v_latch_sp_hi.we;
1333
   release dut.reg_file_.b2v_latch_sp_lo.db;
1334
   release dut.reg_file_.b2v_latch_sp_hi.db;
1335
   // Preset wz
1336
   force dut.reg_file_.b2v_latch_wz_lo.we=1;
1337
   force dut.reg_file_.b2v_latch_wz_hi.we=1;
1338
   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
1339
   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
1340
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
1341
   release dut.reg_file_.b2v_latch_wz_hi.we;
1342
   release dut.reg_file_.b2v_latch_wz_lo.db;
1343
   release dut.reg_file_.b2v_latch_wz_hi.db;
1344
   // Preset pc
1345
   force dut.reg_file_.b2v_latch_pc_lo.we=1;
1346
   force dut.reg_file_.b2v_latch_pc_hi.we=1;
1347
   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
1348
   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
1349
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
1350
   release dut.reg_file_.b2v_latch_pc_hi.we;
1351
   release dut.reg_file_.b2v_latch_pc_lo.db;
1352
   release dut.reg_file_.b2v_latch_pc_hi.db;
1353
   // Preset ir
1354
   force dut.reg_file_.b2v_latch_ir_lo.we=1;
1355
   force dut.reg_file_.b2v_latch_ir_hi.we=1;
1356
   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
1357
   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
1358
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
1359
   release dut.reg_file_.b2v_latch_ir_hi.we;
1360
   release dut.reg_file_.b2v_latch_ir_lo.db;
1361
   release dut.reg_file_.b2v_latch_ir_hi.db;
1362
   // Preset memory
1363
   ram.Mem[0] = 8'h8c;
1364
   // Preset memory
1365
   ram.Mem[56486] = 8'h49;
1366
   force dut.z80_top_ifc_n.fpga_reset=0;
1367
   force dut.address_latch_.abus=16'h0000;
1368
   release dut.reg_control_.ctl_reg_sys_we;
1369
   release dut.reg_file_.reg_gp_we;
1370
#3
1371
   release dut.address_latch_.abus;
1372
#1
1373
#6 // Execute
1374
   force dut.reg_control_.ctl_reg_sys_we=0;
1375
#2 pc=z.A;
1376
#2
1377
#1 force dut.reg_file_.reg_gp_we=0;
1378
   force dut.z80_top_ifc_n.fpga_reset=1;
1379
   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h91) $fdisplay(f,"* Reg af f=%h !=91",dut.reg_file_.b2v_latch_af_lo.latch);
1380
   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hd1) $fdisplay(f,"* Reg af a=%h !=d1",dut.reg_file_.b2v_latch_af_hi.latch);
1381
   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
1382
   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
1383
   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
1384
   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
1385
   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
1386
   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
1387
   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
1388
   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
1389
   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
1390
   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
1391
   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
1392
   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
1393
   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
1394
   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
1395
   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
1396
   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
1397
   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
1398
   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
1399
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
1400
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
1401
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
1402
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
1403
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
1404
//--------------------------------------------------------------------------------
1405
   force dut.instruction_reg_.ctl_ir_we=1;
1406
   force dut.instruction_reg_.db=0;
1407
#2 release dut.instruction_reg_.ctl_ir_we;
1408
   release dut.instruction_reg_.db;
1409
$fdisplay(f,"Testing opcode 92      SUB D");
1410
   // Preset af
1411
   force dut.reg_file_.b2v_latch_af_lo.we=1;
1412
   force dut.reg_file_.b2v_latch_af_hi.we=1;
1413
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
1414
   force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
1415
#2 release dut.reg_file_.b2v_latch_af_lo.we;
1416
   release dut.reg_file_.b2v_latch_af_hi.we;
1417
   release dut.reg_file_.b2v_latch_af_lo.db;
1418
   release dut.reg_file_.b2v_latch_af_hi.db;
1419
   // Preset bc
1420
   force dut.reg_file_.b2v_latch_bc_lo.we=1;
1421
   force dut.reg_file_.b2v_latch_bc_hi.we=1;
1422
   force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
1423
   force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
1424
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
1425
   release dut.reg_file_.b2v_latch_bc_hi.we;
1426
   release dut.reg_file_.b2v_latch_bc_lo.db;
1427
   release dut.reg_file_.b2v_latch_bc_hi.db;
1428
   // Preset de
1429
   force dut.reg_file_.b2v_latch_de_lo.we=1;
1430
   force dut.reg_file_.b2v_latch_de_hi.we=1;
1431
   force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
1432
   force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
1433
#2 release dut.reg_file_.b2v_latch_de_lo.we;
1434
   release dut.reg_file_.b2v_latch_de_hi.we;
1435
   release dut.reg_file_.b2v_latch_de_lo.db;
1436
   release dut.reg_file_.b2v_latch_de_hi.db;
1437
   // Preset hl
1438
   force dut.reg_file_.b2v_latch_hl_lo.we=1;
1439
   force dut.reg_file_.b2v_latch_hl_hi.we=1;
1440
   force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
1441
   force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
1442
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
1443
   release dut.reg_file_.b2v_latch_hl_hi.we;
1444
   release dut.reg_file_.b2v_latch_hl_lo.db;
1445
   release dut.reg_file_.b2v_latch_hl_hi.db;
1446
   // Preset af2
1447
   force dut.reg_file_.b2v_latch_af2_lo.we=1;
1448
   force dut.reg_file_.b2v_latch_af2_hi.we=1;
1449
   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
1450
   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
1451
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
1452
   release dut.reg_file_.b2v_latch_af2_hi.we;
1453
   release dut.reg_file_.b2v_latch_af2_lo.db;
1454
   release dut.reg_file_.b2v_latch_af2_hi.db;
1455
   // Preset bc2
1456
   force dut.reg_file_.b2v_latch_bc2_lo.we=1;
1457
   force dut.reg_file_.b2v_latch_bc2_hi.we=1;
1458
   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
1459
   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
1460
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
1461
   release dut.reg_file_.b2v_latch_bc2_hi.we;
1462
   release dut.reg_file_.b2v_latch_bc2_lo.db;
1463
   release dut.reg_file_.b2v_latch_bc2_hi.db;
1464
   // Preset de2
1465
   force dut.reg_file_.b2v_latch_de2_lo.we=1;
1466
   force dut.reg_file_.b2v_latch_de2_hi.we=1;
1467
   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
1468
   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
1469
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
1470
   release dut.reg_file_.b2v_latch_de2_hi.we;
1471
   release dut.reg_file_.b2v_latch_de2_lo.db;
1472
   release dut.reg_file_.b2v_latch_de2_hi.db;
1473
   // Preset hl2
1474
   force dut.reg_file_.b2v_latch_hl2_lo.we=1;
1475
   force dut.reg_file_.b2v_latch_hl2_hi.we=1;
1476
   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
1477
   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
1478
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
1479
   release dut.reg_file_.b2v_latch_hl2_hi.we;
1480
   release dut.reg_file_.b2v_latch_hl2_lo.db;
1481
   release dut.reg_file_.b2v_latch_hl2_hi.db;
1482
   // Preset ix
1483
   force dut.reg_file_.b2v_latch_ix_lo.we=1;
1484
   force dut.reg_file_.b2v_latch_ix_hi.we=1;
1485
   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
1486
   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
1487
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
1488
   release dut.reg_file_.b2v_latch_ix_hi.we;
1489
   release dut.reg_file_.b2v_latch_ix_lo.db;
1490
   release dut.reg_file_.b2v_latch_ix_hi.db;
1491
   // Preset iy
1492
   force dut.reg_file_.b2v_latch_iy_lo.we=1;
1493
   force dut.reg_file_.b2v_latch_iy_hi.we=1;
1494
   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
1495
   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
1496
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
1497
   release dut.reg_file_.b2v_latch_iy_hi.we;
1498
   release dut.reg_file_.b2v_latch_iy_lo.db;
1499
   release dut.reg_file_.b2v_latch_iy_hi.db;
1500
   // Preset sp
1501
   force dut.reg_file_.b2v_latch_sp_lo.we=1;
1502
   force dut.reg_file_.b2v_latch_sp_hi.we=1;
1503
   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
1504
   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
1505
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
1506
   release dut.reg_file_.b2v_latch_sp_hi.we;
1507
   release dut.reg_file_.b2v_latch_sp_lo.db;
1508
   release dut.reg_file_.b2v_latch_sp_hi.db;
1509
   // Preset wz
1510
   force dut.reg_file_.b2v_latch_wz_lo.we=1;
1511
   force dut.reg_file_.b2v_latch_wz_hi.we=1;
1512
   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
1513
   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
1514
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
1515
   release dut.reg_file_.b2v_latch_wz_hi.we;
1516
   release dut.reg_file_.b2v_latch_wz_lo.db;
1517
   release dut.reg_file_.b2v_latch_wz_hi.db;
1518
   // Preset pc
1519
   force dut.reg_file_.b2v_latch_pc_lo.we=1;
1520
   force dut.reg_file_.b2v_latch_pc_hi.we=1;
1521
   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
1522
   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
1523
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
1524
   release dut.reg_file_.b2v_latch_pc_hi.we;
1525
   release dut.reg_file_.b2v_latch_pc_lo.db;
1526
   release dut.reg_file_.b2v_latch_pc_hi.db;
1527
   // Preset ir
1528
   force dut.reg_file_.b2v_latch_ir_lo.we=1;
1529
   force dut.reg_file_.b2v_latch_ir_hi.we=1;
1530
   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
1531
   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
1532
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
1533
   release dut.reg_file_.b2v_latch_ir_hi.we;
1534
   release dut.reg_file_.b2v_latch_ir_lo.db;
1535
   release dut.reg_file_.b2v_latch_ir_hi.db;
1536
   // Preset memory
1537
   ram.Mem[0] = 8'h92;
1538
   // Preset memory
1539
   ram.Mem[56486] = 8'h49;
1540
   force dut.z80_top_ifc_n.fpga_reset=0;
1541
   force dut.address_latch_.abus=16'h0000;
1542
   release dut.reg_control_.ctl_reg_sys_we;
1543
   release dut.reg_file_.reg_gp_we;
1544
#3
1545
   release dut.address_latch_.abus;
1546
#1
1547
#6 // Execute
1548
   force dut.reg_control_.ctl_reg_sys_we=0;
1549
#2 pc=z.A;
1550
#2
1551
#1 force dut.reg_file_.reg_gp_we=0;
1552
   force dut.z80_top_ifc_n.fpga_reset=1;
1553
   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h82) $fdisplay(f,"* Reg af f=%h !=82",dut.reg_file_.b2v_latch_af_lo.latch);
1554
   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hd5) $fdisplay(f,"* Reg af a=%h !=d5",dut.reg_file_.b2v_latch_af_hi.latch);
1555
   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
1556
   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
1557
   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
1558
   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
1559
   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
1560
   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
1561
   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
1562
   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
1563
   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
1564
   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
1565
   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
1566
   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
1567
   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
1568
   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
1569
   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
1570
   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
1571
   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
1572
   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
1573
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
1574
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
1575
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
1576
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
1577
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
1578
//--------------------------------------------------------------------------------
1579
   force dut.instruction_reg_.ctl_ir_we=1;
1580
   force dut.instruction_reg_.db=0;
1581
#2 release dut.instruction_reg_.ctl_ir_we;
1582
   release dut.instruction_reg_.db;
1583
$fdisplay(f,"Testing opcode 9d      SBC A,L");
1584
   // Preset af
1585
   force dut.reg_file_.b2v_latch_af_lo.we=1;
1586
   force dut.reg_file_.b2v_latch_af_hi.we=1;
1587
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
1588
   force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
1589
#2 release dut.reg_file_.b2v_latch_af_lo.we;
1590
   release dut.reg_file_.b2v_latch_af_hi.we;
1591
   release dut.reg_file_.b2v_latch_af_lo.db;
1592
   release dut.reg_file_.b2v_latch_af_hi.db;
1593
   // Preset bc
1594
   force dut.reg_file_.b2v_latch_bc_lo.we=1;
1595
   force dut.reg_file_.b2v_latch_bc_hi.we=1;
1596
   force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
1597
   force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
1598
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
1599
   release dut.reg_file_.b2v_latch_bc_hi.we;
1600
   release dut.reg_file_.b2v_latch_bc_lo.db;
1601
   release dut.reg_file_.b2v_latch_bc_hi.db;
1602
   // Preset de
1603
   force dut.reg_file_.b2v_latch_de_lo.we=1;
1604
   force dut.reg_file_.b2v_latch_de_hi.we=1;
1605
   force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
1606
   force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
1607
#2 release dut.reg_file_.b2v_latch_de_lo.we;
1608
   release dut.reg_file_.b2v_latch_de_hi.we;
1609
   release dut.reg_file_.b2v_latch_de_lo.db;
1610
   release dut.reg_file_.b2v_latch_de_hi.db;
1611
   // Preset hl
1612
   force dut.reg_file_.b2v_latch_hl_lo.we=1;
1613
   force dut.reg_file_.b2v_latch_hl_hi.we=1;
1614
   force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
1615
   force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
1616
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
1617
   release dut.reg_file_.b2v_latch_hl_hi.we;
1618
   release dut.reg_file_.b2v_latch_hl_lo.db;
1619
   release dut.reg_file_.b2v_latch_hl_hi.db;
1620
   // Preset af2
1621
   force dut.reg_file_.b2v_latch_af2_lo.we=1;
1622
   force dut.reg_file_.b2v_latch_af2_hi.we=1;
1623
   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
1624
   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
1625
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
1626
   release dut.reg_file_.b2v_latch_af2_hi.we;
1627
   release dut.reg_file_.b2v_latch_af2_lo.db;
1628
   release dut.reg_file_.b2v_latch_af2_hi.db;
1629
   // Preset bc2
1630
   force dut.reg_file_.b2v_latch_bc2_lo.we=1;
1631
   force dut.reg_file_.b2v_latch_bc2_hi.we=1;
1632
   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
1633
   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
1634
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
1635
   release dut.reg_file_.b2v_latch_bc2_hi.we;
1636
   release dut.reg_file_.b2v_latch_bc2_lo.db;
1637
   release dut.reg_file_.b2v_latch_bc2_hi.db;
1638
   // Preset de2
1639
   force dut.reg_file_.b2v_latch_de2_lo.we=1;
1640
   force dut.reg_file_.b2v_latch_de2_hi.we=1;
1641
   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
1642
   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
1643
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
1644
   release dut.reg_file_.b2v_latch_de2_hi.we;
1645
   release dut.reg_file_.b2v_latch_de2_lo.db;
1646
   release dut.reg_file_.b2v_latch_de2_hi.db;
1647
   // Preset hl2
1648
   force dut.reg_file_.b2v_latch_hl2_lo.we=1;
1649
   force dut.reg_file_.b2v_latch_hl2_hi.we=1;
1650
   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
1651
   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
1652
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
1653
   release dut.reg_file_.b2v_latch_hl2_hi.we;
1654
   release dut.reg_file_.b2v_latch_hl2_lo.db;
1655
   release dut.reg_file_.b2v_latch_hl2_hi.db;
1656
   // Preset ix
1657
   force dut.reg_file_.b2v_latch_ix_lo.we=1;
1658
   force dut.reg_file_.b2v_latch_ix_hi.we=1;
1659
   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
1660
   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
1661
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
1662
   release dut.reg_file_.b2v_latch_ix_hi.we;
1663
   release dut.reg_file_.b2v_latch_ix_lo.db;
1664
   release dut.reg_file_.b2v_latch_ix_hi.db;
1665
   // Preset iy
1666
   force dut.reg_file_.b2v_latch_iy_lo.we=1;
1667
   force dut.reg_file_.b2v_latch_iy_hi.we=1;
1668
   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
1669
   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
1670
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
1671
   release dut.reg_file_.b2v_latch_iy_hi.we;
1672
   release dut.reg_file_.b2v_latch_iy_lo.db;
1673
   release dut.reg_file_.b2v_latch_iy_hi.db;
1674
   // Preset sp
1675
   force dut.reg_file_.b2v_latch_sp_lo.we=1;
1676
   force dut.reg_file_.b2v_latch_sp_hi.we=1;
1677
   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
1678
   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
1679
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
1680
   release dut.reg_file_.b2v_latch_sp_hi.we;
1681
   release dut.reg_file_.b2v_latch_sp_lo.db;
1682
   release dut.reg_file_.b2v_latch_sp_hi.db;
1683
   // Preset wz
1684
   force dut.reg_file_.b2v_latch_wz_lo.we=1;
1685
   force dut.reg_file_.b2v_latch_wz_hi.we=1;
1686
   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
1687
   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
1688
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
1689
   release dut.reg_file_.b2v_latch_wz_hi.we;
1690
   release dut.reg_file_.b2v_latch_wz_lo.db;
1691
   release dut.reg_file_.b2v_latch_wz_hi.db;
1692
   // Preset pc
1693
   force dut.reg_file_.b2v_latch_pc_lo.we=1;
1694
   force dut.reg_file_.b2v_latch_pc_hi.we=1;
1695
   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
1696
   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
1697
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
1698
   release dut.reg_file_.b2v_latch_pc_hi.we;
1699
   release dut.reg_file_.b2v_latch_pc_lo.db;
1700
   release dut.reg_file_.b2v_latch_pc_hi.db;
1701
   // Preset ir
1702
   force dut.reg_file_.b2v_latch_ir_lo.we=1;
1703
   force dut.reg_file_.b2v_latch_ir_hi.we=1;
1704
   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
1705
   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
1706
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
1707
   release dut.reg_file_.b2v_latch_ir_hi.we;
1708
   release dut.reg_file_.b2v_latch_ir_lo.db;
1709
   release dut.reg_file_.b2v_latch_ir_hi.db;
1710
   // Preset memory
1711
   ram.Mem[0] = 8'h9d;
1712
   // Preset memory
1713
   ram.Mem[56486] = 8'h49;
1714
   force dut.z80_top_ifc_n.fpga_reset=0;
1715
   force dut.address_latch_.abus=16'h0000;
1716
   release dut.reg_control_.ctl_reg_sys_we;
1717
   release dut.reg_file_.reg_gp_we;
1718
#3
1719
   release dut.address_latch_.abus;
1720
#1
1721
#6 // Execute
1722
   force dut.reg_control_.ctl_reg_sys_we=0;
1723
#2 pc=z.A;
1724
#2
1725
#1 force dut.reg_file_.reg_gp_we=0;
1726
   force dut.z80_top_ifc_n.fpga_reset=1;
1727
   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h1a) $fdisplay(f,"* Reg af f=%h !=1a",dut.reg_file_.b2v_latch_af_lo.latch);
1728
   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h4f) $fdisplay(f,"* Reg af a=%h !=4f",dut.reg_file_.b2v_latch_af_hi.latch);
1729
   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
1730
   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
1731
   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
1732
   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
1733
   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
1734
   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
1735
   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
1736
   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
1737
   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
1738
   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
1739
   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
1740
   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
1741
   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
1742
   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
1743
   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
1744
   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
1745
   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
1746
   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
1747
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
1748
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
1749
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
1750
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
1751
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
1752
//--------------------------------------------------------------------------------
1753
   force dut.instruction_reg_.ctl_ir_we=1;
1754
   force dut.instruction_reg_.db=0;
1755
#2 release dut.instruction_reg_.ctl_ir_we;
1756
   release dut.instruction_reg_.db;
1757
$fdisplay(f,"Testing opcode a3      AND E");
1758
   // Preset af
1759
   force dut.reg_file_.b2v_latch_af_lo.we=1;
1760
   force dut.reg_file_.b2v_latch_af_hi.we=1;
1761
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
1762
   force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
1763
#2 release dut.reg_file_.b2v_latch_af_lo.we;
1764
   release dut.reg_file_.b2v_latch_af_hi.we;
1765
   release dut.reg_file_.b2v_latch_af_lo.db;
1766
   release dut.reg_file_.b2v_latch_af_hi.db;
1767
   // Preset bc
1768
   force dut.reg_file_.b2v_latch_bc_lo.we=1;
1769
   force dut.reg_file_.b2v_latch_bc_hi.we=1;
1770
   force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
1771
   force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
1772
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
1773
   release dut.reg_file_.b2v_latch_bc_hi.we;
1774
   release dut.reg_file_.b2v_latch_bc_lo.db;
1775
   release dut.reg_file_.b2v_latch_bc_hi.db;
1776
   // Preset de
1777
   force dut.reg_file_.b2v_latch_de_lo.we=1;
1778
   force dut.reg_file_.b2v_latch_de_hi.we=1;
1779
   force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
1780
   force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
1781
#2 release dut.reg_file_.b2v_latch_de_lo.we;
1782
   release dut.reg_file_.b2v_latch_de_hi.we;
1783
   release dut.reg_file_.b2v_latch_de_lo.db;
1784
   release dut.reg_file_.b2v_latch_de_hi.db;
1785
   // Preset hl
1786
   force dut.reg_file_.b2v_latch_hl_lo.we=1;
1787
   force dut.reg_file_.b2v_latch_hl_hi.we=1;
1788
   force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
1789
   force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
1790
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
1791
   release dut.reg_file_.b2v_latch_hl_hi.we;
1792
   release dut.reg_file_.b2v_latch_hl_lo.db;
1793
   release dut.reg_file_.b2v_latch_hl_hi.db;
1794
   // Preset af2
1795
   force dut.reg_file_.b2v_latch_af2_lo.we=1;
1796
   force dut.reg_file_.b2v_latch_af2_hi.we=1;
1797
   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
1798
   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
1799
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
1800
   release dut.reg_file_.b2v_latch_af2_hi.we;
1801
   release dut.reg_file_.b2v_latch_af2_lo.db;
1802
   release dut.reg_file_.b2v_latch_af2_hi.db;
1803
   // Preset bc2
1804
   force dut.reg_file_.b2v_latch_bc2_lo.we=1;
1805
   force dut.reg_file_.b2v_latch_bc2_hi.we=1;
1806
   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
1807
   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
1808
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
1809
   release dut.reg_file_.b2v_latch_bc2_hi.we;
1810
   release dut.reg_file_.b2v_latch_bc2_lo.db;
1811
   release dut.reg_file_.b2v_latch_bc2_hi.db;
1812
   // Preset de2
1813
   force dut.reg_file_.b2v_latch_de2_lo.we=1;
1814
   force dut.reg_file_.b2v_latch_de2_hi.we=1;
1815
   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
1816
   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
1817
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
1818
   release dut.reg_file_.b2v_latch_de2_hi.we;
1819
   release dut.reg_file_.b2v_latch_de2_lo.db;
1820
   release dut.reg_file_.b2v_latch_de2_hi.db;
1821
   // Preset hl2
1822
   force dut.reg_file_.b2v_latch_hl2_lo.we=1;
1823
   force dut.reg_file_.b2v_latch_hl2_hi.we=1;
1824
   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
1825
   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
1826
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
1827
   release dut.reg_file_.b2v_latch_hl2_hi.we;
1828
   release dut.reg_file_.b2v_latch_hl2_lo.db;
1829
   release dut.reg_file_.b2v_latch_hl2_hi.db;
1830
   // Preset ix
1831
   force dut.reg_file_.b2v_latch_ix_lo.we=1;
1832
   force dut.reg_file_.b2v_latch_ix_hi.we=1;
1833
   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
1834
   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
1835
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
1836
   release dut.reg_file_.b2v_latch_ix_hi.we;
1837
   release dut.reg_file_.b2v_latch_ix_lo.db;
1838
   release dut.reg_file_.b2v_latch_ix_hi.db;
1839
   // Preset iy
1840
   force dut.reg_file_.b2v_latch_iy_lo.we=1;
1841
   force dut.reg_file_.b2v_latch_iy_hi.we=1;
1842
   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
1843
   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
1844
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
1845
   release dut.reg_file_.b2v_latch_iy_hi.we;
1846
   release dut.reg_file_.b2v_latch_iy_lo.db;
1847
   release dut.reg_file_.b2v_latch_iy_hi.db;
1848
   // Preset sp
1849
   force dut.reg_file_.b2v_latch_sp_lo.we=1;
1850
   force dut.reg_file_.b2v_latch_sp_hi.we=1;
1851
   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
1852
   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
1853
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
1854
   release dut.reg_file_.b2v_latch_sp_hi.we;
1855
   release dut.reg_file_.b2v_latch_sp_lo.db;
1856
   release dut.reg_file_.b2v_latch_sp_hi.db;
1857
   // Preset wz
1858
   force dut.reg_file_.b2v_latch_wz_lo.we=1;
1859
   force dut.reg_file_.b2v_latch_wz_hi.we=1;
1860
   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
1861
   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
1862
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
1863
   release dut.reg_file_.b2v_latch_wz_hi.we;
1864
   release dut.reg_file_.b2v_latch_wz_lo.db;
1865
   release dut.reg_file_.b2v_latch_wz_hi.db;
1866
   // Preset pc
1867
   force dut.reg_file_.b2v_latch_pc_lo.we=1;
1868
   force dut.reg_file_.b2v_latch_pc_hi.we=1;
1869
   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
1870
   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
1871
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
1872
   release dut.reg_file_.b2v_latch_pc_hi.we;
1873
   release dut.reg_file_.b2v_latch_pc_lo.db;
1874
   release dut.reg_file_.b2v_latch_pc_hi.db;
1875
   // Preset ir
1876
   force dut.reg_file_.b2v_latch_ir_lo.we=1;
1877
   force dut.reg_file_.b2v_latch_ir_hi.we=1;
1878
   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
1879
   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
1880
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
1881
   release dut.reg_file_.b2v_latch_ir_hi.we;
1882
   release dut.reg_file_.b2v_latch_ir_lo.db;
1883
   release dut.reg_file_.b2v_latch_ir_hi.db;
1884
   // Preset memory
1885
   ram.Mem[0] = 8'ha3;
1886
   // Preset memory
1887
   ram.Mem[56486] = 8'h49;
1888
   force dut.z80_top_ifc_n.fpga_reset=0;
1889
   force dut.address_latch_.abus=16'h0000;
1890
   release dut.reg_control_.ctl_reg_sys_we;
1891
   release dut.reg_file_.reg_gp_we;
1892
#3
1893
   release dut.address_latch_.abus;
1894
#1
1895
#6 // Execute
1896
   force dut.reg_control_.ctl_reg_sys_we=0;
1897
#2 pc=z.A;
1898
#2
1899
#1 force dut.reg_file_.reg_gp_we=0;
1900
   force dut.z80_top_ifc_n.fpga_reset=1;
1901
   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h14) $fdisplay(f,"* Reg af f=%h !=14",dut.reg_file_.b2v_latch_af_lo.latch);
1902
   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h05) $fdisplay(f,"* Reg af a=%h !=05",dut.reg_file_.b2v_latch_af_hi.latch);
1903
   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
1904
   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
1905
   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
1906
   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
1907
   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
1908
   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
1909
   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
1910
   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
1911
   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
1912
   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
1913
   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
1914
   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
1915
   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
1916
   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
1917
   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
1918
   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
1919
   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
1920
   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
1921
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
1922
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
1923
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
1924
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
1925
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
1926
//--------------------------------------------------------------------------------
1927
   force dut.instruction_reg_.ctl_ir_we=1;
1928
   force dut.instruction_reg_.db=0;
1929
#2 release dut.instruction_reg_.ctl_ir_we;
1930
   release dut.instruction_reg_.db;
1931
$fdisplay(f,"Testing opcode ae      XOR (HL)");
1932
   // Preset af
1933
   force dut.reg_file_.b2v_latch_af_lo.we=1;
1934
   force dut.reg_file_.b2v_latch_af_hi.we=1;
1935
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
1936
   force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
1937
#2 release dut.reg_file_.b2v_latch_af_lo.we;
1938
   release dut.reg_file_.b2v_latch_af_hi.we;
1939
   release dut.reg_file_.b2v_latch_af_lo.db;
1940
   release dut.reg_file_.b2v_latch_af_hi.db;
1941
   // Preset bc
1942
   force dut.reg_file_.b2v_latch_bc_lo.we=1;
1943
   force dut.reg_file_.b2v_latch_bc_hi.we=1;
1944
   force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
1945
   force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
1946
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
1947
   release dut.reg_file_.b2v_latch_bc_hi.we;
1948
   release dut.reg_file_.b2v_latch_bc_lo.db;
1949
   release dut.reg_file_.b2v_latch_bc_hi.db;
1950
   // Preset de
1951
   force dut.reg_file_.b2v_latch_de_lo.we=1;
1952
   force dut.reg_file_.b2v_latch_de_hi.we=1;
1953
   force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
1954
   force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
1955
#2 release dut.reg_file_.b2v_latch_de_lo.we;
1956
   release dut.reg_file_.b2v_latch_de_hi.we;
1957
   release dut.reg_file_.b2v_latch_de_lo.db;
1958
   release dut.reg_file_.b2v_latch_de_hi.db;
1959
   // Preset hl
1960
   force dut.reg_file_.b2v_latch_hl_lo.we=1;
1961
   force dut.reg_file_.b2v_latch_hl_hi.we=1;
1962
   force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
1963
   force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
1964
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
1965
   release dut.reg_file_.b2v_latch_hl_hi.we;
1966
   release dut.reg_file_.b2v_latch_hl_lo.db;
1967
   release dut.reg_file_.b2v_latch_hl_hi.db;
1968
   // Preset af2
1969
   force dut.reg_file_.b2v_latch_af2_lo.we=1;
1970
   force dut.reg_file_.b2v_latch_af2_hi.we=1;
1971
   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
1972
   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
1973
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
1974
   release dut.reg_file_.b2v_latch_af2_hi.we;
1975
   release dut.reg_file_.b2v_latch_af2_lo.db;
1976
   release dut.reg_file_.b2v_latch_af2_hi.db;
1977
   // Preset bc2
1978
   force dut.reg_file_.b2v_latch_bc2_lo.we=1;
1979
   force dut.reg_file_.b2v_latch_bc2_hi.we=1;
1980
   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
1981
   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
1982
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
1983
   release dut.reg_file_.b2v_latch_bc2_hi.we;
1984
   release dut.reg_file_.b2v_latch_bc2_lo.db;
1985
   release dut.reg_file_.b2v_latch_bc2_hi.db;
1986
   // Preset de2
1987
   force dut.reg_file_.b2v_latch_de2_lo.we=1;
1988
   force dut.reg_file_.b2v_latch_de2_hi.we=1;
1989
   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
1990
   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
1991
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
1992
   release dut.reg_file_.b2v_latch_de2_hi.we;
1993
   release dut.reg_file_.b2v_latch_de2_lo.db;
1994
   release dut.reg_file_.b2v_latch_de2_hi.db;
1995
   // Preset hl2
1996
   force dut.reg_file_.b2v_latch_hl2_lo.we=1;
1997
   force dut.reg_file_.b2v_latch_hl2_hi.we=1;
1998
   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
1999
   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
2000
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
2001
   release dut.reg_file_.b2v_latch_hl2_hi.we;
2002
   release dut.reg_file_.b2v_latch_hl2_lo.db;
2003
   release dut.reg_file_.b2v_latch_hl2_hi.db;
2004
   // Preset ix
2005
   force dut.reg_file_.b2v_latch_ix_lo.we=1;
2006
   force dut.reg_file_.b2v_latch_ix_hi.we=1;
2007
   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
2008
   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
2009
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
2010
   release dut.reg_file_.b2v_latch_ix_hi.we;
2011
   release dut.reg_file_.b2v_latch_ix_lo.db;
2012
   release dut.reg_file_.b2v_latch_ix_hi.db;
2013
   // Preset iy
2014
   force dut.reg_file_.b2v_latch_iy_lo.we=1;
2015
   force dut.reg_file_.b2v_latch_iy_hi.we=1;
2016
   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
2017
   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
2018
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
2019
   release dut.reg_file_.b2v_latch_iy_hi.we;
2020
   release dut.reg_file_.b2v_latch_iy_lo.db;
2021
   release dut.reg_file_.b2v_latch_iy_hi.db;
2022
   // Preset sp
2023
   force dut.reg_file_.b2v_latch_sp_lo.we=1;
2024
   force dut.reg_file_.b2v_latch_sp_hi.we=1;
2025
   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
2026
   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
2027
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
2028
   release dut.reg_file_.b2v_latch_sp_hi.we;
2029
   release dut.reg_file_.b2v_latch_sp_lo.db;
2030
   release dut.reg_file_.b2v_latch_sp_hi.db;
2031
   // Preset wz
2032
   force dut.reg_file_.b2v_latch_wz_lo.we=1;
2033
   force dut.reg_file_.b2v_latch_wz_hi.we=1;
2034
   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
2035
   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
2036
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
2037
   release dut.reg_file_.b2v_latch_wz_hi.we;
2038
   release dut.reg_file_.b2v_latch_wz_lo.db;
2039
   release dut.reg_file_.b2v_latch_wz_hi.db;
2040
   // Preset pc
2041
   force dut.reg_file_.b2v_latch_pc_lo.we=1;
2042
   force dut.reg_file_.b2v_latch_pc_hi.we=1;
2043
   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
2044
   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
2045
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
2046
   release dut.reg_file_.b2v_latch_pc_hi.we;
2047
   release dut.reg_file_.b2v_latch_pc_lo.db;
2048
   release dut.reg_file_.b2v_latch_pc_hi.db;
2049
   // Preset ir
2050
   force dut.reg_file_.b2v_latch_ir_lo.we=1;
2051
   force dut.reg_file_.b2v_latch_ir_hi.we=1;
2052
   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
2053
   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
2054
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
2055
   release dut.reg_file_.b2v_latch_ir_hi.we;
2056
   release dut.reg_file_.b2v_latch_ir_lo.db;
2057
   release dut.reg_file_.b2v_latch_ir_hi.db;
2058
   // Preset memory
2059
   ram.Mem[0] = 8'hae;
2060
   // Preset memory
2061
   ram.Mem[56486] = 8'h49;
2062
   force dut.z80_top_ifc_n.fpga_reset=0;
2063
   force dut.address_latch_.abus=16'h0000;
2064
   release dut.reg_control_.ctl_reg_sys_we;
2065
   release dut.reg_file_.reg_gp_we;
2066
#3
2067
   release dut.address_latch_.abus;
2068
#1
2069
#12 // Execute
2070
   force dut.reg_control_.ctl_reg_sys_we=0;
2071
#2 pc=z.A;
2072
#2
2073
#1 force dut.reg_file_.reg_gp_we=0;
2074
   force dut.z80_top_ifc_n.fpga_reset=1;
2075
   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'ha8) $fdisplay(f,"* Reg af f=%h !=a8",dut.reg_file_.b2v_latch_af_lo.latch);
2076
   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hbc) $fdisplay(f,"* Reg af a=%h !=bc",dut.reg_file_.b2v_latch_af_hi.latch);
2077
   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
2078
   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
2079
   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
2080
   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
2081
   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
2082
   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
2083
   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
2084
   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
2085
   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
2086
   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
2087
   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
2088
   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
2089
   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
2090
   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
2091
   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
2092
   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
2093
   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
2094
   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
2095
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
2096
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
2097
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
2098
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
2099
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
2100
//--------------------------------------------------------------------------------
2101
   force dut.instruction_reg_.ctl_ir_we=1;
2102
   force dut.instruction_reg_.db=0;
2103
#2 release dut.instruction_reg_.ctl_ir_we;
2104
   release dut.instruction_reg_.db;
2105
$fdisplay(f,"Testing opcode b4      OR H");
2106
   // Preset af
2107
   force dut.reg_file_.b2v_latch_af_lo.we=1;
2108
   force dut.reg_file_.b2v_latch_af_hi.we=1;
2109
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
2110
   force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
2111
#2 release dut.reg_file_.b2v_latch_af_lo.we;
2112
   release dut.reg_file_.b2v_latch_af_hi.we;
2113
   release dut.reg_file_.b2v_latch_af_lo.db;
2114
   release dut.reg_file_.b2v_latch_af_hi.db;
2115
   // Preset bc
2116
   force dut.reg_file_.b2v_latch_bc_lo.we=1;
2117
   force dut.reg_file_.b2v_latch_bc_hi.we=1;
2118
   force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
2119
   force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
2120
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
2121
   release dut.reg_file_.b2v_latch_bc_hi.we;
2122
   release dut.reg_file_.b2v_latch_bc_lo.db;
2123
   release dut.reg_file_.b2v_latch_bc_hi.db;
2124
   // Preset de
2125
   force dut.reg_file_.b2v_latch_de_lo.we=1;
2126
   force dut.reg_file_.b2v_latch_de_hi.we=1;
2127
   force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
2128
   force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
2129
#2 release dut.reg_file_.b2v_latch_de_lo.we;
2130
   release dut.reg_file_.b2v_latch_de_hi.we;
2131
   release dut.reg_file_.b2v_latch_de_lo.db;
2132
   release dut.reg_file_.b2v_latch_de_hi.db;
2133
   // Preset hl
2134
   force dut.reg_file_.b2v_latch_hl_lo.we=1;
2135
   force dut.reg_file_.b2v_latch_hl_hi.we=1;
2136
   force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
2137
   force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
2138
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
2139
   release dut.reg_file_.b2v_latch_hl_hi.we;
2140
   release dut.reg_file_.b2v_latch_hl_lo.db;
2141
   release dut.reg_file_.b2v_latch_hl_hi.db;
2142
   // Preset af2
2143
   force dut.reg_file_.b2v_latch_af2_lo.we=1;
2144
   force dut.reg_file_.b2v_latch_af2_hi.we=1;
2145
   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
2146
   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
2147
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
2148
   release dut.reg_file_.b2v_latch_af2_hi.we;
2149
   release dut.reg_file_.b2v_latch_af2_lo.db;
2150
   release dut.reg_file_.b2v_latch_af2_hi.db;
2151
   // Preset bc2
2152
   force dut.reg_file_.b2v_latch_bc2_lo.we=1;
2153
   force dut.reg_file_.b2v_latch_bc2_hi.we=1;
2154
   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
2155
   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
2156
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
2157
   release dut.reg_file_.b2v_latch_bc2_hi.we;
2158
   release dut.reg_file_.b2v_latch_bc2_lo.db;
2159
   release dut.reg_file_.b2v_latch_bc2_hi.db;
2160
   // Preset de2
2161
   force dut.reg_file_.b2v_latch_de2_lo.we=1;
2162
   force dut.reg_file_.b2v_latch_de2_hi.we=1;
2163
   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
2164
   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
2165
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
2166
   release dut.reg_file_.b2v_latch_de2_hi.we;
2167
   release dut.reg_file_.b2v_latch_de2_lo.db;
2168
   release dut.reg_file_.b2v_latch_de2_hi.db;
2169
   // Preset hl2
2170
   force dut.reg_file_.b2v_latch_hl2_lo.we=1;
2171
   force dut.reg_file_.b2v_latch_hl2_hi.we=1;
2172
   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
2173
   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
2174
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
2175
   release dut.reg_file_.b2v_latch_hl2_hi.we;
2176
   release dut.reg_file_.b2v_latch_hl2_lo.db;
2177
   release dut.reg_file_.b2v_latch_hl2_hi.db;
2178
   // Preset ix
2179
   force dut.reg_file_.b2v_latch_ix_lo.we=1;
2180
   force dut.reg_file_.b2v_latch_ix_hi.we=1;
2181
   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
2182
   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
2183
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
2184
   release dut.reg_file_.b2v_latch_ix_hi.we;
2185
   release dut.reg_file_.b2v_latch_ix_lo.db;
2186
   release dut.reg_file_.b2v_latch_ix_hi.db;
2187
   // Preset iy
2188
   force dut.reg_file_.b2v_latch_iy_lo.we=1;
2189
   force dut.reg_file_.b2v_latch_iy_hi.we=1;
2190
   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
2191
   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
2192
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
2193
   release dut.reg_file_.b2v_latch_iy_hi.we;
2194
   release dut.reg_file_.b2v_latch_iy_lo.db;
2195
   release dut.reg_file_.b2v_latch_iy_hi.db;
2196
   // Preset sp
2197
   force dut.reg_file_.b2v_latch_sp_lo.we=1;
2198
   force dut.reg_file_.b2v_latch_sp_hi.we=1;
2199
   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
2200
   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
2201
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
2202
   release dut.reg_file_.b2v_latch_sp_hi.we;
2203
   release dut.reg_file_.b2v_latch_sp_lo.db;
2204
   release dut.reg_file_.b2v_latch_sp_hi.db;
2205
   // Preset wz
2206
   force dut.reg_file_.b2v_latch_wz_lo.we=1;
2207
   force dut.reg_file_.b2v_latch_wz_hi.we=1;
2208
   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
2209
   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
2210
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
2211
   release dut.reg_file_.b2v_latch_wz_hi.we;
2212
   release dut.reg_file_.b2v_latch_wz_lo.db;
2213
   release dut.reg_file_.b2v_latch_wz_hi.db;
2214
   // Preset pc
2215
   force dut.reg_file_.b2v_latch_pc_lo.we=1;
2216
   force dut.reg_file_.b2v_latch_pc_hi.we=1;
2217
   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
2218
   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
2219
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
2220
   release dut.reg_file_.b2v_latch_pc_hi.we;
2221
   release dut.reg_file_.b2v_latch_pc_lo.db;
2222
   release dut.reg_file_.b2v_latch_pc_hi.db;
2223
   // Preset ir
2224
   force dut.reg_file_.b2v_latch_ir_lo.we=1;
2225
   force dut.reg_file_.b2v_latch_ir_hi.we=1;
2226
   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
2227
   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
2228
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
2229
   release dut.reg_file_.b2v_latch_ir_hi.we;
2230
   release dut.reg_file_.b2v_latch_ir_lo.db;
2231
   release dut.reg_file_.b2v_latch_ir_hi.db;
2232
   // Preset memory
2233
   ram.Mem[0] = 8'hb4;
2234
   // Preset memory
2235
   ram.Mem[56486] = 8'h49;
2236
   force dut.z80_top_ifc_n.fpga_reset=0;
2237
   force dut.address_latch_.abus=16'h0000;
2238
   release dut.reg_control_.ctl_reg_sys_we;
2239
   release dut.reg_file_.reg_gp_we;
2240
#3
2241
   release dut.address_latch_.abus;
2242
#1
2243
#6 // Execute
2244
   force dut.reg_control_.ctl_reg_sys_we=0;
2245
#2 pc=z.A;
2246
#2
2247
#1 force dut.reg_file_.reg_gp_we=0;
2248
   force dut.z80_top_ifc_n.fpga_reset=1;
2249
   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'ha8) $fdisplay(f,"* Reg af f=%h !=a8",dut.reg_file_.b2v_latch_af_lo.latch);
2250
   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hfd) $fdisplay(f,"* Reg af a=%h !=fd",dut.reg_file_.b2v_latch_af_hi.latch);
2251
   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
2252
   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
2253
   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
2254
   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
2255
   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
2256
   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
2257
   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
2258
   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
2259
   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
2260
   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
2261
   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
2262
   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
2263
   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
2264
   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
2265
   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
2266
   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
2267
   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
2268
   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
2269
   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
2270
   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
2271
   if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
2272
   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
2273
   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
2274
//--------------------------------------------------------------------------------
2275
   force dut.instruction_reg_.ctl_ir_we=1;
2276
   force dut.instruction_reg_.db=0;
2277
#2 release dut.instruction_reg_.ctl_ir_we;
2278
   release dut.instruction_reg_.db;
2279
$fdisplay(f,"Testing opcode bf      CP A");
2280
   // Preset af
2281
   force dut.reg_file_.b2v_latch_af_lo.we=1;
2282
   force dut.reg_file_.b2v_latch_af_hi.we=1;
2283
   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
2284
   force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
2285
#2 release dut.reg_file_.b2v_latch_af_lo.we;
2286
   release dut.reg_file_.b2v_latch_af_hi.we;
2287
   release dut.reg_file_.b2v_latch_af_lo.db;
2288
   release dut.reg_file_.b2v_latch_af_hi.db;
2289
   // Preset bc
2290
   force dut.reg_file_.b2v_latch_bc_lo.we=1;
2291
   force dut.reg_file_.b2v_latch_bc_hi.we=1;
2292
   force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
2293
   force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
2294
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
2295
   release dut.reg_file_.b2v_latch_bc_hi.we;
2296
   release dut.reg_file_.b2v_latch_bc_lo.db;
2297
   release dut.reg_file_.b2v_latch_bc_hi.db;
2298
   // Preset de
2299
   force dut.reg_file_.b2v_latch_de_lo.we=1;
2300
   force dut.reg_file_.b2v_latch_de_hi.we=1;
2301
   force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
2302
   force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
2303
#2 release dut.reg_file_.b2v_latch_de_lo.we;
2304
   release dut.reg_file_.b2v_latch_de_hi.we;
2305
   release dut.reg_file_.b2v_latch_de_lo.db;
2306
   release dut.reg_file_.b2v_latch_de_hi.db;
2307
   // Preset hl
2308
   force dut.reg_file_.b2v_latch_hl_lo.we=1;
2309
   force dut.reg_file_.b2v_latch_hl_hi.we=1;
2310
   force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
2311
   force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
2312
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
2313
   release dut.reg_file_.b2v_latch_hl_hi.we;
2314
   release dut.reg_file_.b2v_latch_hl_lo.db;
2315
   release dut.reg_file_.b2v_latch_hl_hi.db;
2316
   // Preset af2
2317
   force dut.reg_file_.b2v_latch_af2_lo.we=1;
2318
   force dut.reg_file_.b2v_latch_af2_hi.we=1;
2319
   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
2320
   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
2321
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
2322
   release dut.reg_file_.b2v_latch_af2_hi.we;
2323
   release dut.reg_file_.b2v_latch_af2_lo.db;
2324
   release dut.reg_file_.b2v_latch_af2_hi.db;
2325
   // Preset bc2
2326
   force dut.reg_file_.b2v_latch_bc2_lo.we=1;
2327
   force dut.reg_file_.b2v_latch_bc2_hi.we=1;
2328
   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
2329
   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
2330
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
2331
   release dut.reg_file_.b2v_latch_bc2_hi.we;
2332
   release dut.reg_file_.b2v_latch_bc2_lo.db;
2333
   release dut.reg_file_.b2v_latch_bc2_hi.db;
2334
   // Preset de2
2335
   force dut.reg_file_.b2v_latch_de2_lo.we=1;
2336
   force dut.reg_file_.b2v_latch_de2_hi.we=1;
2337
   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
2338
   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
2339
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
2340
   release dut.reg_file_.b2v_latch_de2_hi.we;
2341
   release dut.reg_file_.b2v_latch_de2_lo.db;
2342
   release dut.reg_file_.b2v_latch_de2_hi.db;
2343
   // Preset hl2
2344
   force dut.reg_file_.b2v_latch_hl2_lo.we=1;
2345
   force dut.reg_file_.b2v_latch_hl2_hi.we=1;
2346
   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
2347
   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
2348
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
2349
   release dut.reg_file_.b2v_latch_hl2_hi.we;
2350
   release dut.reg_file_.b2v_latch_hl2_lo.db;
2351
   release dut.reg_file_.b2v_latch_hl2_hi.db;
2352
   // Preset ix
2353
   force dut.reg_file_.b2v_latch_ix_lo.we=1;
2354
   force dut.reg_file_.b2v_latch_ix_hi.we=1;
2355
   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
2356
   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
2357
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
2358
   release dut.reg_file_.b2v_latch_ix_hi.we;
2359
   release dut.reg_file_.b2v_latch_ix_lo.db;
2360
   release dut.reg_file_.b2v_latch_ix_hi.db;
2361
   // Preset iy
2362
   force dut.reg_file_.b2v_latch_iy_lo.we=1;
2363
   force dut.reg_file_.b2v_latch_iy_hi.we=1;
2364
   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
2365
   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
2366
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
2367
   release dut.reg_file_.b2v_latch_iy_hi.we;
2368
   release dut.reg_file_.b2v_latch_iy_lo.db;
2369
   release dut.reg_file_.b2v_latch_iy_hi.db;
2370
   // Preset sp
2371
   force dut.reg_file_.b2v_latch_sp_lo.we=1;
2372
   force dut.reg_file_.b2v_latch_sp_hi.we=1;
2373
   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
2374
   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
2375
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
2376
   release dut.reg_file_.b2v_latch_sp_hi.we;
2377
   release dut.reg_file_.b2v_latch_sp_lo.db;
2378
   release dut.reg_file_.b2v_latch_sp_hi.db;
2379
   // Preset wz
2380
   force dut.reg_file_.b2v_latch_wz_lo.we=1;
2381
   force dut.reg_file_.b2v_latch_wz_hi.we=1;
2382
   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
2383
   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
2384
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
2385
   release dut.reg_file_.b2v_latch_wz_hi.we;
2386
   release dut.reg_file_.b2v_latch_wz_lo.db;
2387
   release dut.reg_file_.b2v_latch_wz_hi.db;
2388
   // Preset pc
2389
   force dut.reg_file_.b2v_latch_pc_lo.we=1;
2390
   force dut.reg_file_.b2v_latch_pc_hi.we=1;
2391
   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
2392
   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
2393
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
2394
   release dut.reg_file_.b2v_latch_pc_hi.we;
2395
   release dut.reg_file_.b2v_latch_pc_lo.db;
2396
   release dut.reg_file_.b2v_latch_pc_hi.db;
2397
   // Preset ir
2398
   force dut.reg_file_.b2v_latch_ir_lo.we=1;
2399
   force dut.reg_file_.b2v_latch_ir_hi.we=1;
2400
   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
2401
   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
2402
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
2403
   release dut.reg_file_.b2v_latch_ir_hi.we;
2404
   release dut.reg_file_.b2v_latch_ir_lo.db;
2405
   release dut.reg_file_.b2v_latch_ir_hi.db;
2406
   // Preset memory
2407
   ram.Mem[0] = 8'hbf;
2408
   // Preset memory
2409
   ram.Mem[56486] =