OpenCores
URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

Subversion Repositories a-z80

[/] [a-z80/] [trunk/] [host/] [basic_de1/] [test_host.sv] - Blame information for rev 8

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 8 gdevic
//--------------------------------------------------------------
2
// Testbench for the host board
3
//--------------------------------------------------------------
4
`timescale 10 ns/ 10 ns
5
 
6
module test_bench_host();
7
 
8
reg reset;
9
reg nint;
10
reg nnmi;
11
wire uart_tx;
12
 
13
// Proper sequence for the ModelSim reset
14
initial begin : init
15
    reset = 0;
16
    nint = 1;
17
    nnmi = 1;
18
#10 reset = 1;
19
end : init
20
 
21
reg clk = 1;
22
initial forever #1 clk = ~clk;
23
 
24
host host_( .nint(nint), .nnmi(nnmi), .clk(clk), .reset(reset), .uart_tx(uart_tx) );
25
 
26
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.