1 |
8 |
gdevic |
// file: clock.v
|
2 |
|
|
//
|
3 |
|
|
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
4 |
|
|
//
|
5 |
|
|
// This file contains confidential and proprietary information
|
6 |
|
|
// of Xilinx, Inc. and is protected under U.S. and
|
7 |
|
|
// international copyright and other intellectual property
|
8 |
|
|
// laws.
|
9 |
|
|
//
|
10 |
|
|
// DISCLAIMER
|
11 |
|
|
// This disclaimer is not a license and does not grant any
|
12 |
|
|
// rights to the materials distributed herewith. Except as
|
13 |
|
|
// otherwise provided in a valid license issued to you by
|
14 |
|
|
// Xilinx, and to the maximum extent permitted by applicable
|
15 |
|
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
16 |
|
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
17 |
|
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
18 |
|
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
19 |
|
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
20 |
|
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
21 |
|
|
// including negligence, or under any other theory of
|
22 |
|
|
// liability) for any loss or damage of any kind or nature
|
23 |
|
|
// related to, arising under or in connection with these
|
24 |
|
|
// materials, including for any direct, or any indirect,
|
25 |
|
|
// special, incidental, or consequential loss or damage
|
26 |
|
|
// (including loss of data, profits, goodwill, or any type of
|
27 |
|
|
// loss or damage suffered as a result of any action brought
|
28 |
|
|
// by a third party) even if such damage or loss was
|
29 |
|
|
// reasonably foreseeable or Xilinx had been advised of the
|
30 |
|
|
// possibility of the same.
|
31 |
|
|
//
|
32 |
|
|
// CRITICAL APPLICATIONS
|
33 |
|
|
// Xilinx products are not designed or intended to be fail-
|
34 |
|
|
// safe, or for use in any application requiring fail-safe
|
35 |
|
|
// performance, such as life-support or safety devices or
|
36 |
|
|
// systems, Class III medical devices, nuclear facilities,
|
37 |
|
|
// applications related to the deployment of airbags, or any
|
38 |
|
|
// other applications that could lead to death, personal
|
39 |
|
|
// injury, or severe property or environmental damage
|
40 |
|
|
// (individually and collectively, "Critical
|
41 |
|
|
// Applications"). Customer assumes the sole risk and
|
42 |
|
|
// liability of any use of Xilinx products in Critical
|
43 |
|
|
// Applications, subject only to applicable laws and
|
44 |
|
|
// regulations governing limitations on product liability.
|
45 |
|
|
//
|
46 |
|
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
47 |
|
|
// PART OF THIS FILE AT ALL TIMES.
|
48 |
|
|
//
|
49 |
|
|
//----------------------------------------------------------------------------
|
50 |
|
|
// User entered comments
|
51 |
|
|
//----------------------------------------------------------------------------
|
52 |
|
|
// None
|
53 |
|
|
//
|
54 |
|
|
//----------------------------------------------------------------------------
|
55 |
|
|
// "Output Output Phase Duty Pk-to-Pk Phase"
|
56 |
|
|
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
57 |
|
|
//----------------------------------------------------------------------------
|
58 |
|
|
// CLK_OUT1____10.000______0.000______50.0_____1200.000____150.000
|
59 |
|
|
// CLK_OUT2____50.000______0.000______50.0______200.000____150.000
|
60 |
|
|
//
|
61 |
|
|
//----------------------------------------------------------------------------
|
62 |
|
|
// "Input Clock Freq (MHz) Input Jitter (UI)"
|
63 |
|
|
//----------------------------------------------------------------------------
|
64 |
|
|
// __primary_________100.000____________0.010
|
65 |
|
|
|
66 |
|
|
`timescale 1ps/1ps
|
67 |
|
|
|
68 |
|
|
(* CORE_GENERATION_INFO = "clock,clk_wiz_v3_6,{component_name=clock,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
|
69 |
|
|
module clock
|
70 |
|
|
(// Clock in ports
|
71 |
|
|
input CLK_IN1,
|
72 |
|
|
// Clock out ports
|
73 |
|
|
output CLK_OUT1,
|
74 |
|
|
output CLK_OUT2,
|
75 |
|
|
// Status and control signals
|
76 |
|
|
output LOCKED
|
77 |
|
|
);
|
78 |
|
|
|
79 |
|
|
// Input buffering
|
80 |
|
|
//------------------------------------
|
81 |
|
|
IBUFG clkin1_buf
|
82 |
|
|
(.O (clkin1),
|
83 |
|
|
.I (CLK_IN1));
|
84 |
|
|
|
85 |
|
|
|
86 |
|
|
// Clocking primitive
|
87 |
|
|
//------------------------------------
|
88 |
|
|
|
89 |
|
|
// Instantiation of the DCM primitive
|
90 |
|
|
// * Unused inputs are tied off
|
91 |
|
|
// * Unused outputs are labeled unused
|
92 |
|
|
wire psdone_unused;
|
93 |
|
|
wire locked_int;
|
94 |
|
|
wire [7:0] status_int;
|
95 |
|
|
wire clkfb;
|
96 |
|
|
wire clk0;
|
97 |
|
|
wire clkfx;
|
98 |
|
|
|
99 |
|
|
DCM_SP
|
100 |
|
|
#(.CLKDV_DIVIDE (5.000),
|
101 |
|
|
.CLKFX_DIVIDE (10),
|
102 |
|
|
.CLKFX_MULTIPLY (2),
|
103 |
|
|
.CLKIN_DIVIDE_BY_2 ("TRUE"),
|
104 |
|
|
.CLKIN_PERIOD (10.0),
|
105 |
|
|
.CLKOUT_PHASE_SHIFT ("NONE"),
|
106 |
|
|
.CLK_FEEDBACK ("1X"),
|
107 |
|
|
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
|
108 |
|
|
.PHASE_SHIFT (0),
|
109 |
|
|
.STARTUP_WAIT ("FALSE"))
|
110 |
|
|
dcm_sp_inst
|
111 |
|
|
// Input clock
|
112 |
|
|
(.CLKIN (clkin1),
|
113 |
|
|
.CLKFB (clkfb),
|
114 |
|
|
// Output clocks
|
115 |
|
|
.CLK0 (clk0),
|
116 |
|
|
.CLK90 (),
|
117 |
|
|
.CLK180 (),
|
118 |
|
|
.CLK270 (),
|
119 |
|
|
.CLK2X (),
|
120 |
|
|
.CLK2X180 (),
|
121 |
|
|
.CLKFX (clkfx),
|
122 |
|
|
.CLKFX180 (),
|
123 |
|
|
.CLKDV (),
|
124 |
|
|
// Ports for dynamic phase shift
|
125 |
|
|
.PSCLK (1'b0),
|
126 |
|
|
.PSEN (1'b0),
|
127 |
|
|
.PSINCDEC (1'b0),
|
128 |
|
|
.PSDONE (),
|
129 |
|
|
// Other control and status signals
|
130 |
|
|
.LOCKED (locked_int),
|
131 |
|
|
.STATUS (status_int),
|
132 |
|
|
.RST (1'b0),
|
133 |
|
|
// Unused pin- tie low
|
134 |
|
|
.DSSEN (1'b0));
|
135 |
|
|
|
136 |
|
|
assign LOCKED = locked_int;
|
137 |
|
|
|
138 |
|
|
// Output buffering
|
139 |
|
|
//-----------------------------------
|
140 |
|
|
assign clkfb = CLK_OUT2;
|
141 |
|
|
|
142 |
|
|
BUFG clkout1_buf
|
143 |
|
|
(.O (CLK_OUT1),
|
144 |
|
|
.I (clkfx));
|
145 |
|
|
|
146 |
|
|
|
147 |
|
|
BUFG clkout2_buf
|
148 |
|
|
(.O (CLK_OUT2),
|
149 |
|
|
.I (clk0));
|
150 |
|
|
|
151 |
|
|
|
152 |
|
|
|
153 |
|
|
endmodule
|