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gdevic |
##############################################################
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#
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# Xilinx Core Generator version 14.7
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# Date: Sat Mar 05 15:25:10 2016
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# Generated from component: xilinx.com:ip:clk_wiz:3.6
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = Verilog
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SET device = xc6slx16
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SET devicefamily = spartan6
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = csg324
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -2
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SET verilogsim = true
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SET vhdlsim = false
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# END Project Options
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# BEGIN Select
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SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
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# END Select
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# BEGIN Parameters
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CSET calc_done=DONE
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CSET clk_in_sel_port=CLK_IN_SEL
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CSET clk_out1_port=CLK_OUT1
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CSET clk_out1_use_fine_ps_gui=false
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CSET clk_out2_port=CLK_OUT2
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CSET clk_out2_use_fine_ps_gui=false
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CSET clk_out3_port=CLK_OUT3
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CSET clk_out3_use_fine_ps_gui=false
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CSET clk_out4_port=CLK_OUT4
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CSET clk_out4_use_fine_ps_gui=false
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CSET clk_out5_port=CLK_OUT5
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CSET clk_out5_use_fine_ps_gui=false
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CSET clk_out6_port=CLK_OUT6
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CSET clk_out6_use_fine_ps_gui=false
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CSET clk_out7_port=CLK_OUT7
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CSET clk_out7_use_fine_ps_gui=false
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CSET clk_valid_port=CLK_VALID
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CSET clkfb_in_n_port=CLKFB_IN_N
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CSET clkfb_in_p_port=CLKFB_IN_P
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CSET clkfb_in_port=CLKFB_IN
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CSET clkfb_in_signaling=SINGLE
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CSET clkfb_out_n_port=CLKFB_OUT_N
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CSET clkfb_out_p_port=CLKFB_OUT_P
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CSET clkfb_out_port=CLKFB_OUT
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CSET clkfb_stopped_port=CLKFB_STOPPED
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CSET clkin1_jitter_ps=100.0
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CSET clkin1_ui_jitter=0.010
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CSET clkin2_jitter_ps=100.0
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CSET clkin2_ui_jitter=0.010
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CSET clkout1_drives=BUFG
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CSET clkout1_requested_duty_cycle=50.000
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CSET clkout1_requested_out_freq=10
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CSET clkout1_requested_phase=0.000
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CSET clkout2_drives=BUFG
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CSET clkout2_requested_duty_cycle=50.000
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CSET clkout2_requested_out_freq=50
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CSET clkout2_requested_phase=0.000
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CSET clkout2_used=true
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CSET clkout3_drives=BUFG
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CSET clkout3_requested_duty_cycle=50.000
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CSET clkout3_requested_out_freq=100
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CSET clkout3_requested_phase=0.000
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CSET clkout3_used=false
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CSET clkout4_drives=BUFG
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CSET clkout4_requested_duty_cycle=50.000
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CSET clkout4_requested_out_freq=100.000
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CSET clkout4_requested_phase=0.000
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CSET clkout4_used=false
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CSET clkout5_drives=BUFG
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CSET clkout5_requested_duty_cycle=50.000
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CSET clkout5_requested_out_freq=100.000
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CSET clkout5_requested_phase=0.000
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CSET clkout5_used=false
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CSET clkout6_drives=BUFG
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CSET clkout6_requested_duty_cycle=50.000
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CSET clkout6_requested_out_freq=100.000
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CSET clkout6_requested_phase=0.000
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CSET clkout6_used=false
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CSET clkout7_drives=BUFG
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CSET clkout7_requested_duty_cycle=50.000
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CSET clkout7_requested_out_freq=100.000
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CSET clkout7_requested_phase=0.000
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CSET clkout7_used=false
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CSET clock_mgr_type=AUTO
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CSET component_name=clock
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CSET daddr_port=DADDR
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CSET dclk_port=DCLK
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CSET dcm_clk_feedback=1X
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CSET dcm_clk_out1_port=CLKFX
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CSET dcm_clk_out2_port=CLK0
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CSET dcm_clk_out3_port=CLK2X
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CSET dcm_clk_out4_port=CLK0
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CSET dcm_clk_out5_port=CLK0
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CSET dcm_clk_out6_port=CLK0
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CSET dcm_clkdv_divide=5.0
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CSET dcm_clkfx_divide=10
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CSET dcm_clkfx_multiply=2
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CSET dcm_clkgen_clk_out1_port=CLKFX
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CSET dcm_clkgen_clk_out2_port=CLKFX
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CSET dcm_clkgen_clk_out3_port=CLKFX
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CSET dcm_clkgen_clkfx_divide=1
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CSET dcm_clkgen_clkfx_md_max=0.000
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CSET dcm_clkgen_clkfx_multiply=4
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CSET dcm_clkgen_clkfxdv_divide=2
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CSET dcm_clkgen_clkin_period=10.000
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CSET dcm_clkgen_notes=None
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CSET dcm_clkgen_spread_spectrum=NONE
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CSET dcm_clkgen_startup_wait=false
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CSET dcm_clkin_divide_by_2=true
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CSET dcm_clkin_period=10.000
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CSET dcm_clkout_phase_shift=NONE
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CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
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CSET dcm_notes=None
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CSET dcm_phase_shift=0
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CSET dcm_pll_cascade=NONE
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CSET dcm_startup_wait=false
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CSET den_port=DEN
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CSET din_port=DIN
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CSET dout_port=DOUT
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CSET drdy_port=DRDY
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CSET dwe_port=DWE
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CSET feedback_source=FDBK_AUTO
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CSET in_freq_units=Units_MHz
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CSET in_jitter_units=Units_UI
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CSET input_clk_stopped_port=INPUT_CLK_STOPPED
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CSET jitter_options=UI
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CSET jitter_sel=No_Jitter
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CSET locked_port=LOCKED
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CSET mmcm_bandwidth=OPTIMIZED
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CSET mmcm_clkfbout_mult_f=4.000
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CSET mmcm_clkfbout_phase=0.000
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CSET mmcm_clkfbout_use_fine_ps=false
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CSET mmcm_clkin1_period=10.000
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CSET mmcm_clkin2_period=10.000
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CSET mmcm_clkout0_divide_f=4.000
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CSET mmcm_clkout0_duty_cycle=0.500
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CSET mmcm_clkout0_phase=0.000
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CSET mmcm_clkout0_use_fine_ps=false
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CSET mmcm_clkout1_divide=1
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CSET mmcm_clkout1_duty_cycle=0.500
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CSET mmcm_clkout1_phase=0.000
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CSET mmcm_clkout1_use_fine_ps=false
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CSET mmcm_clkout2_divide=1
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CSET mmcm_clkout2_duty_cycle=0.500
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CSET mmcm_clkout2_phase=0.000
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CSET mmcm_clkout2_use_fine_ps=false
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CSET mmcm_clkout3_divide=1
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CSET mmcm_clkout3_duty_cycle=0.500
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CSET mmcm_clkout3_phase=0.000
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CSET mmcm_clkout3_use_fine_ps=false
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CSET mmcm_clkout4_cascade=false
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CSET mmcm_clkout4_divide=1
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CSET mmcm_clkout4_duty_cycle=0.500
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CSET mmcm_clkout4_phase=0.000
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CSET mmcm_clkout4_use_fine_ps=false
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CSET mmcm_clkout5_divide=1
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CSET mmcm_clkout5_duty_cycle=0.500
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CSET mmcm_clkout5_phase=0.000
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CSET mmcm_clkout5_use_fine_ps=false
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CSET mmcm_clkout6_divide=1
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CSET mmcm_clkout6_duty_cycle=0.500
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CSET mmcm_clkout6_phase=0.000
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CSET mmcm_clkout6_use_fine_ps=false
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CSET mmcm_clock_hold=false
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CSET mmcm_compensation=ZHOLD
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CSET mmcm_divclk_divide=1
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CSET mmcm_notes=None
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CSET mmcm_ref_jitter1=0.010
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CSET mmcm_ref_jitter2=0.010
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CSET mmcm_startup_wait=false
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CSET num_out_clks=2
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CSET override_dcm=false
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CSET override_dcm_clkgen=false
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CSET override_mmcm=false
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CSET override_pll=false
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CSET platform=nt64
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CSET pll_bandwidth=OPTIMIZED
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CSET pll_clk_feedback=CLKFBOUT
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CSET pll_clkfbout_mult=4
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CSET pll_clkfbout_phase=0.000
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CSET pll_clkin_period=10.0
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CSET pll_clkout0_divide=40
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CSET pll_clkout0_duty_cycle=0.500
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CSET pll_clkout0_phase=0.000
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CSET pll_clkout1_divide=80
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CSET pll_clkout1_duty_cycle=0.500
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CSET pll_clkout1_phase=0.000
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CSET pll_clkout2_divide=7
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CSET pll_clkout2_duty_cycle=0.500
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CSET pll_clkout2_phase=0.000
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CSET pll_clkout3_divide=1
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CSET pll_clkout3_duty_cycle=0.500
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CSET pll_clkout3_phase=0.000
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CSET pll_clkout4_divide=1
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CSET pll_clkout4_duty_cycle=0.500
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CSET pll_clkout4_phase=0.000
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CSET pll_clkout5_divide=1
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CSET pll_clkout5_duty_cycle=0.500
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CSET pll_clkout5_phase=0.000
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CSET pll_compensation=SYSTEM_SYNCHRONOUS
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CSET pll_divclk_divide=1
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CSET pll_notes=None
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CSET pll_ref_jitter=0.010
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CSET power_down_port=POWER_DOWN
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CSET prim_in_freq=100.000
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CSET prim_in_jitter=0.010
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CSET prim_source=Single_ended_clock_capable_pin
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CSET primary_port=CLK_IN1
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CSET primitive=MMCM
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CSET primtype_sel=PLL_BASE
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CSET psclk_port=PSCLK
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CSET psdone_port=PSDONE
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CSET psen_port=PSEN
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CSET psincdec_port=PSINCDEC
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CSET relative_inclk=REL_PRIMARY
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CSET reset_port=RESET
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CSET secondary_in_freq=100.000
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CSET secondary_in_jitter=0.010
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CSET secondary_port=CLK_IN2
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CSET secondary_source=Single_ended_clock_capable_pin
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CSET ss_mod_freq=250
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CSET ss_mode=CENTER_HIGH
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| 244 |
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CSET status_port=STATUS
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| 245 |
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CSET summary_strings=empty
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| 246 |
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CSET use_clk_valid=false
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| 247 |
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CSET use_clkfb_stopped=false
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| 248 |
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CSET use_dyn_phase_shift=false
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| 249 |
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CSET use_dyn_reconfig=false
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| 250 |
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CSET use_freeze=false
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| 251 |
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CSET use_freq_synth=true
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| 252 |
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CSET use_inclk_stopped=false
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| 253 |
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CSET use_inclk_switchover=false
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| 254 |
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CSET use_locked=true
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| 255 |
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CSET use_max_i_jitter=false
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| 256 |
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CSET use_min_o_jitter=false
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| 257 |
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CSET use_min_power=false
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| 258 |
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CSET use_phase_alignment=true
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| 259 |
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CSET use_power_down=false
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| 260 |
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CSET use_reset=false
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| 261 |
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CSET use_spread_spectrum=false
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CSET use_spread_spectrum_1=false
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CSET use_status=false
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# END Parameters
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# BEGIN Extra information
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MISC pkg_timestamp=2012-05-10T12:44:55Z
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# END Extra information
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GENERATE
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# CRC: de7f6af0
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