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https://opencores.org/ocsvn/a-z80/a-z80/trunk
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gdevic |
#ChipScope Core Generator Project File Version 3.0
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#Tue Feb 23 19:15:38 Central Standard Time 2016
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SignalExport.clockChannel=CLK
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SignalExport.dataChannel<0000>=DATA[0]
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SignalExport.dataChannel<0001>=DATA[1]
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SignalExport.dataChannel<0002>=DATA[2]
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SignalExport.dataChannel<0003>=DATA[3]
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SignalExport.dataChannel<0004>=DATA[4]
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SignalExport.dataChannel<0005>=DATA[5]
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SignalExport.dataChannel<0006>=DATA[6]
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SignalExport.dataChannel<0007>=DATA[7]
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SignalExport.dataEqualsTrigger=false
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SignalExport.dataPortWidth=8
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SignalExport.triggerChannel<0000><0000>=TRIG0[0]
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SignalExport.triggerChannel<0000><0001>=TRIG0[1]
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SignalExport.triggerChannel<0000><0002>=TRIG0[2]
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SignalExport.triggerChannel<0000><0003>=TRIG0[3]
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SignalExport.triggerChannel<0000><0004>=TRIG0[4]
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SignalExport.triggerChannel<0000><0005>=TRIG0[5]
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SignalExport.triggerChannel<0000><0006>=TRIG0[6]
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SignalExport.triggerChannel<0000><0007>=TRIG0[7]
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SignalExport.triggerPort<0000>.name=TRIG0
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SignalExport.triggerPortCount=1
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SignalExport.triggerPortIsData<0000>=false
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SignalExport.triggerPortWidth<0000>=8
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SignalExport.type=ila
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