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[/] [a-z80/] [trunk/] [host/] [basic_nexys3/] [test_host.v] - Blame information for rev 10

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Line No. Rev Author Line
1 8 gdevic
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date:   00:18:56 02/14/2016
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// Design Name:   host
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// Module Name:   R:/Z80/host/basic_nexys3/test_host.v
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// Project Name:  host_nexys3
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: host
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module test_host;
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    // Inputs
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    reg CLOCK_100;
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    reg KEY0;
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    reg KEY1;
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    reg KEY2;
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    // Outputs
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    wire UART_TXD;
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    wire [7:0] GPIO_1;
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    wire [7:0] GPIO_2;
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    // Bidirs
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    wire [7:0] GPIO_0;
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    wire [7:0] GPIO_3;
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    // Instantiate the Unit Under Test (UUT)
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    host uut (
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        .CLOCK_100(CLOCK_100),
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        .KEY0(KEY0),
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        .KEY1(KEY1),
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        .KEY2(KEY2),
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        .UART_TXD(UART_TXD),
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        .GPIO_0(GPIO_0),
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        .GPIO_1(GPIO_1),
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        .GPIO_2(GPIO_2),
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        .GPIO_3(GPIO_3)
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    );
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    initial begin
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        CLOCK_100 = 0;
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        KEY0 = 1;
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        KEY1 = 0;
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        KEY2 = 0;
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        // 100 MHz -> 10MHz (pll) -> div 4 (clk divider)
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        #(100/10*4 * 3); // hold for 3 CPU clock cycles
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        #(100/10*4 * 3); // ...twice, due to the way our CLOCK_100 gen below works
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        KEY0 = 0;
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    end
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    initial begin
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        forever #1 CLOCK_100 = ~CLOCK_100;
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    end
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endmodule
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