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[/] [a-z80/] [trunk/] [host/] [zxspectrum_de1/] [ula/] [i2c_loader.vhd] - Blame information for rev 15

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1 8 gdevic
-- ZX Spectrum for Altera DE1
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--
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-- Copyright (c) 2009-2010 Mike Stirling
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- * Redistributions of source code must retain the above copyright notice,
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--   this list of conditions and the following disclaimer.
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--
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-- * Redistributions in synthesized form must reproduce the above copyright
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--   notice, this list of conditions and the following disclaimer in the
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--   documentation and/or other materials provided with the distribution.
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--
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-- * Neither the name of the author nor the names of other contributors may
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--   be used to endorse or promote products derived from this software without
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--   specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_MISC.ALL; -- for AND_REDUCE
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use IEEE.NUMERIC_STD.ALL;
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entity i2c_loader is
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generic (
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    -- Address of slave to be loaded
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    device_address : integer := 16#1a#;
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    -- Number of retries to allow before stopping
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    num_retries : integer := 0;
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    -- Length of clock divider in bits.  Resulting bus frequency is
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    -- CLK/2^(log2_divider + 2)
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    log2_divider : integer := 6
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);
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port (
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    CLK         :   in  std_logic;
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    nRESET      :   in  std_logic;
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    I2C_SCL     :   inout   std_logic;
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    I2C_SDA     :   inout   std_logic;
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    IS_DONE     :   out std_logic;
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    IS_ERROR    :   out std_logic
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    );
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end i2c_loader;
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architecture i2c_loader_arch of i2c_loader is
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type regs is array(0 to 19) of std_logic_vector(7 downto 0);
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constant init_regs : regs := (
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    -- Left line in, 0dB, unmute
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    X"00", X"17",
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    -- Right line in, 0dB, unmute
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    X"02", X"17",
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    -- Left headphone out, 0dB
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    X"04", X"79",
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    -- Right headphone out, 0dB
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    X"06", X"79",
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    -- Audio path, DAC enabled, Line in, Bypass off, mic unmuted
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    X"08", X"10",
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    -- Digital path, Unmute, HP filter enabled
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    X"0A", X"00",
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    -- Power down mic, clkout and xtal osc
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    X"0C", X"62",
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    -- Format 16-bit I2S, no bit inversion or phase changes
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    X"0E", X"02",
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    -- Sampling control, 8 kHz USB mode (MCLK = 250fs * 6)
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    X"10", X"0D",
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    -- Activate
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    X"12", X"01"
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    );
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-- Number of bursts (i.e. total number of registers)
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constant burst_length : positive := 2;
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-- Number of bytes to transfer per burst
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constant num_bursts : positive := (init_regs'length / burst_length);
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type state_t is (Idle, Start, Data, Ack, Stop, Pause, Done);
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signal state : state_t;
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signal phase : std_logic_vector(1 downto 0);
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subtype nbit_t is integer range 0 to 7;
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signal nbit : nbit_t;
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subtype nbyte_t is integer range 0 to burst_length; -- +1 for address byte
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signal nbyte : nbyte_t;
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subtype thisbyte_t is integer range 0 to init_regs'length; -- +1 for "done"
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signal thisbyte : thisbyte_t;
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subtype retries_t is integer range 0 to num_retries;
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signal retries : retries_t;
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signal clken : std_logic;
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signal divider : std_logic_vector(log2_divider-1 downto 0);
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signal shiftreg : std_logic_vector(7 downto 0);
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signal scl_out : std_logic;
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signal sda_out : std_logic;
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signal nak : std_logic;
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begin
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    -- Create open-drain outputs for I2C bus
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    I2C_SCL <= '0' when scl_out = '0' else 'Z';
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    I2C_SDA <= '0' when sda_out = '0' else 'Z';
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    -- Status outputs are driven both ways
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    IS_DONE <= '1' when state = Done else '0';
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    IS_ERROR <= nak;
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    -- Generate clock enable for desired bus speed
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    clken <= AND_REDUCE(divider);
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    process(nRESET,CLK)
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    begin
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        if nRESET = '0' then
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            divider <= (others => '0');
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        elsif falling_edge(CLK) then
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            divider <= divider + '1';
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        end if;
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    end process;
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    -- The I2C loader process
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    process(nRESET,CLK,clken)
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    begin
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        if nRESET = '0' then
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            scl_out <= '1';
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            sda_out <= '1';
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            state <= Idle;
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            phase <= "00";
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            nbit <= 0;
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            nbyte <= 0;
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            thisbyte <= 0;
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            shiftreg <= (others => '0');
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            nak <= '0'; -- No error
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            retries <= num_retries;
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        elsif rising_edge(CLK) and clken = '1' then
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            -- Next phase by default
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            phase <= phase + 1;
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            -- STATE: IDLE
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            if state = Idle then
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                -- Start loading the device registers straight away
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                -- A 'GO' bit could be polled here if required
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                state <= Start;
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                phase <= "00";
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                scl_out <= '1';
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                sda_out <= '1';
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            -- STATE: START
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            elsif state = Start then
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                -- Generate START condition
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                case phase is
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                when "00" =>
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                    -- Drop SDA first
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                    sda_out <= '0';
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                when "10" =>
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                    -- Then drop SCL
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                    scl_out <= '0';
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                when "11" =>
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                    -- Advance to next state
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                    -- Shift register loaded with device slave address
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                    state <= Data;
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                    nbit <= 7;
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                    shiftreg <= std_logic_vector(to_unsigned(device_address,7)) & '0'; -- writing
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                    nbyte <= burst_length;
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                when others =>
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                    null;
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                end case;
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            -- STATE: DATA
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            elsif state = Data then
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                -- Generate data
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                case phase is
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                when "00" =>
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                    -- Drop SCL
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                    scl_out <= '0';
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                when "01" =>
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                    -- Output data and shift (MSb first)
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                    sda_out <= shiftreg(7);
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                    shiftreg <= shiftreg(6 downto 0) & '0';
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                when "10" =>
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                    -- Raise SCL
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                    scl_out <= '1';
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                when "11" =>
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                    -- Next bit or advance to next state when done
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                    if nbit = 0 then
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                        state <= Ack;
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                    else
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                        nbit <= nbit - 1;
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                    end if;
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                when others =>
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                  null;
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                end case;
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            -- STATE: ACK
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            elsif state = Ack then
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                -- Generate ACK clock and check for error condition
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                case phase is
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                when "00" =>
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                    -- Drop SCL
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                    scl_out <= '0';
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                when "01" =>
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                    -- Float data
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                    sda_out <= '1';
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                when "10" =>
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                    -- Sample ack bit
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                    nak <= I2C_SDA;
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                    if I2C_SDA = '1' then
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                        -- Error
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                        nbyte <= 0; -- Close this burst and skip remaining registers
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                        thisbyte <= init_regs'length;
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                    else
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                        -- Hold ACK to avoid spurious stops - this seems to fix a
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                        -- problem with the Wolfson codec which releases the ACK
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                        -- right on the falling edge of the clock pulse.  It looks like
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                        -- the device interprets this is a STOP condition and then fails
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                        -- to acknowledge the next byte.  We can avoid this by holding the
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                        -- ACK condition for a little longer.
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                        sda_out <= '0';
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                    end if;
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                    -- Raise SCL
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                    scl_out <= '1';
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                when "11" =>
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                    -- Advance to next state
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                    if nbyte = 0 then
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                        -- No more bytes in this burst - generate a STOP
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                        state <= Stop;
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                    else
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                        -- Generate next byte
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                        state <= Data;
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                        nbit <= 7;
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                        shiftreg <= init_regs(thisbyte);
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                        nbyte <= nbyte - 1;
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                        thisbyte <= thisbyte + 1;
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                    end if;
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                when others =>
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                    null;
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                end case;
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            -- STATE: STOP
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            elsif state = Stop then
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                -- Generate STOP condition
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                case phase is
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                when "00" =>
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                    -- Drop SCL first
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                    scl_out <= '0';
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                when "01" =>
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                    -- Drop SDA
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                    sda_out <= '0';
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                when "10" =>
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                    -- Raise SCL
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                    scl_out <= '1';
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                when "11" =>
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                    if thisbyte = init_regs'length then
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                        -- All registers done, advance to finished state.  This will
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                        -- bring SDA high while SCL is still high, completing the STOP
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                        -- condition
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                        state <= Done;
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                    else
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                        -- Load the next register after a short delay
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                        state <= Pause;
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                    end if;
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                when others =>
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                    null;
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                end case;
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            -- STATE: PAUSE
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            elsif state = Pause then
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                -- Delay for one cycle of 'phase' then start the next burst
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                scl_out <= '1';
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                sda_out <= '1';
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                if phase = "11" then
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                    state <= Start;
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                end if;
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            -- STATE: DONE
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            else
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                -- Finished
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                scl_out <= '1';
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                sda_out <= '1';
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                if nak = '1' and retries > 0 then
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                    -- We can retry in the event of a NAK in case the
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                    -- slave got out of sync for some reason
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                    retries <= retries - 1;
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                    state <= Idle;
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                end if;
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            end if;
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        end if;
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    end process;
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end i2c_loader_arch;
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