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gdevic |
//------------------------------------------------------------------------
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// This Arduino sketch should be used with a Mega board connected to a
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// dongle hosting a Z80 CPU. The Arduino fully controls and senses all
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// Z80 CPU pins. This software runs physical Z80 CPU by providing clock
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// ticks and setting various control pins.
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//
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// There is a limited RAM buffer simulated by this sketch. All Z80 memory
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// accesses are directed to use that buffer.
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//
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// Address and data buses from Z80 are connected to analog Arduino pins.
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// Along with a resistor network on the dongle, this allows the software
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// to sense when Z80 tri-states those two buses.
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//
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// Notes:
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// - Use serial set to 115200
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// - In the Arduino serial monitor window, set line ending to "CR"
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// - Memory access is simulated using a 256-byte pseudo-RAM memory
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// - I/O map is _not_ implemented. Reads will return whatever happens
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// to be on the data bus
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//
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// Copyright 2014 by Goran Devic
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// This source code is released under the GPL v2 software license.
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//------------------------------------------------------------------------
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#include
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#include "WString.h"
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// Define Arduino Mega pins that are connected to a Z80 dongle board.
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// Pin numbers appear out-of-order, but they cleanly connect in complete
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// blocks to sets of pins on Arduino Mega! This will become obvious once
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// you start connecting them...
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#define DB0 A9 // DB pin line-up on a Z80 is a bit swizzled...
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#define DB1 A8
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#define DB2 A11
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#define DB3 A14
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#define DB4 A15
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#define DB5 A13
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#define DB6 A12
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#define DB7 A10
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// Address bus pins from Z80 are connected to A0..A7 on Arduino.
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#define INT 52 // This is a block of control signals from the
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#define NMI 50 // bottom-left corner of Z80
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#define HALT 48
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#define MREQ 46
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#define IORQ 44
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#define RFSH 53 // This is a block of control signals from the
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#define M1 51 // bottom-right corner of Z80
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#define RESET 49
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#define BUSRQ 47
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#define WAIT 45
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#define BUSAK 43
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#define WR 41
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#define RD 39
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#define CLK 13 // Clock is also toggling Arduino LED (fast, though)
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// Tri-state detection values: the values that are read on analog pins
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// sensing the "high-Z" will differ based on the resistor values that make
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// up your voltage divider. Print your particular readings and adjust these:
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#define HI_Z_LOW 50 // Upper "0" value; low tri-state boundary
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#define HI_Z_HIGH 600 // Low "1" value; upper tri-state boundary
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// Control *output* pins of Z80, we read them into these variables
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int halt;
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int mreq;
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int iorq;
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int rfsh;
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int m1;
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int busak;
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int wr;
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int rd;
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// Control *input* pins of Z80, we write them into the dongle
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int zint = 1;
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int nmi = 1;
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int reset = 1;
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int busrq = 1;
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int wait = 1;
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// Content of address and data wires
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int ab;
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byte db;
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// Clock counter after reset
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int clkCount;
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int clkCountHi;
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// T-cycle counter
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int T;
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int Mlast;
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// M1-cycle counter
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int m1Count;
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// Detection if the address or data bus is tri-stated
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bool abTristated = false;
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bool dbTristated = false;
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// Simulation control variables
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bool running = 1; // Simulation is running or is stopped
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int traceShowBothPhases; // Show both phases of a clock cycle
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int traceRefresh; // Trace refresh cycles
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int tracePause; // Pause for a key press every so many clocks
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int tracePauseCount; // Current clock count for tracePause
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int stopAtClk; // Stop the simulation after this many clocks
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int stopAtM1; // Stop at a specific M1 cycle number
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int stopAtHalt; // Stop when HALT signal gets active
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int intAtClk; // Issue INT signal at that clock number
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int nmiAtClk; // Issue NMI signal at that clock number
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int busrqAtClk; // Issue BUSRQ signal at that clock number
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int resetAtClk; // Issue RESET signal at that clock number
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int waitAtClk; // Issue WAIT signal at that clock number
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int clearAtClk; // Clear all control signals at that clock number
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byte iorqVector; // Push IORQ vector (default is FF)
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// Buffer containing RAM memory for Z80 to access
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byte ram[256];
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// Temp buffer to store input line
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#define TEMP_SIZE 512
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char temp[TEMP_SIZE];
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// Temp buffer to store extra dump information
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char extraInfo[64] = { "" };
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// Utility function to provide a meaningful printf to a serial port
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void p(char *fmt, ... ){
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char tmp[256]; // resulting string limited to 256 chars
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va_list args;
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va_start (args, fmt );
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vsnprintf(tmp, 256, fmt, args);
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va_end (args);
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Serial.print(tmp);
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}
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// Read and return one ASCII hex value from a string
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byte hex(char *s){
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byte nibbleH = (*s - '0') & ~(1<<5);
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byte nibbleL = (*(s+1) - '0') & ~(1<<5);
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if (nibbleH>9) nibbleH -= 7;
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if (nibbleL>9) nibbleL -= 7;
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return (nibbleH << 4) | nibbleL;
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}
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// Read and return one ASCII hex value from a temp buffer given the index
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// of that hex number. This is used only to read Intel HEX format buffer.
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byte hexFromTemp(char *pTemp, int index)
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{
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int start = (index*2)+1;
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return hex(pTemp + start);
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}
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// -----------------------------------------------------------
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// Arduino initialization entry point
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// -----------------------------------------------------------
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void setup()
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{
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Serial.begin(115200);
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Serial.flush();
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Serial.setTimeout(1000*60*60);
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ResetSimulationVars();
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// By default, all Arduino pins are set as inputs
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// Configure all output pins, *inputs* into Z80
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pinMode(CLK, OUTPUT);
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digitalWrite(CLK, HIGH);
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pinMode(INT, OUTPUT);
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pinMode(NMI, OUTPUT);
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pinMode(RESET, OUTPUT);
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pinMode(BUSRQ, OUTPUT);
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pinMode(WAIT, OUTPUT);
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WriteControlPins();
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// Perform a Z80 CPU reset
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DoReset();
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}
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// Resets all simulation variables to their defaults
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void ResetSimulationVars()
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{
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traceShowBothPhases = 0;// Show both phases of a clock cycle
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traceRefresh = 1; // Trace refresh cycles
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tracePause = -1; // Pause for a keypress every so many clocks
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stopAtClk = 40; // Stop the simulation after this many clocks
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stopAtM1 = -1; // Stop at a specific M1 cycle number
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stopAtHalt = 1; // Stop when HALT signal gets active
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intAtClk = -1; // Issue INT signal at that clock number
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nmiAtClk = -1; // Issue NMI signal at that clock number
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busrqAtClk = -1; // Issue BUSRQ signal at that clock number
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resetAtClk = -1; // Issue RESET signal at that clock number
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waitAtClk = -1; // Issue WAIT signal at that clock number
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clearAtClk = -1; // Clear all control signals at that clock number
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iorqVector = 0xFF; // Push IORQ vector
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}
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// Issue a RESET sequence to Z80 and reset internal counters
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void DoReset()
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{
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p("\r\n:Starting the clock\r\n");
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digitalWrite(RESET, LOW); delay(1);
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// Reset should be kept low for 3 full clock cycles
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for(int i=0; i<3; i++)
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{
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digitalWrite(CLK, HIGH); delay(1);
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digitalWrite(CLK, LOW); delay(1);
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}
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p(":Releasing RESET\r\n");
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digitalWrite(RESET, HIGH); delay(1);
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// Do not count initial 2 clocks after the reset
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clkCount = -2;
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T = 0;
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Mlast = 1;
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tracePauseCount = 0;
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m1Count = 0;
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}
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// Write all control pins into the Z80 dongle
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void WriteControlPins()
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{
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digitalWrite(INT, zint ? HIGH : LOW);
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digitalWrite(NMI, nmi ? HIGH : LOW);
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digitalWrite(RESET, reset ? HIGH : LOW);
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digitalWrite(BUSRQ, busrq ? HIGH : LOW);
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digitalWrite(WAIT, wait ? HIGH : LOW);
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}
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// Set new data value into the Z80 data bus
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void SetDataToDB(byte data)
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{
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pinMode(DB0, OUTPUT);
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pinMode(DB1, OUTPUT);
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pinMode(DB2, OUTPUT);
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pinMode(DB3, OUTPUT);
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pinMode(DB4, OUTPUT);
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pinMode(DB5, OUTPUT);
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pinMode(DB6, OUTPUT);
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pinMode(DB7, OUTPUT);
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digitalWrite(DB0, (data & (1<<0)) ? HIGH : LOW);
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digitalWrite(DB1, (data & (1<<1)) ? HIGH : LOW);
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digitalWrite(DB2, (data & (1<<2)) ? HIGH : LOW);
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digitalWrite(DB3, (data & (1<<3)) ? HIGH : LOW);
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digitalWrite(DB4, (data & (1<<4)) ? HIGH : LOW);
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digitalWrite(DB5, (data & (1<<5)) ? HIGH : LOW);
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digitalWrite(DB6, (data & (1<<6)) ? HIGH : LOW);
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digitalWrite(DB7, (data & (1<<7)) ? HIGH : LOW);
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db = data;
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dbTristated = false;
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}
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// Read Z80 data bus and store into db variable
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void GetDataFromDB()
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{
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pinMode(DB0, INPUT);
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pinMode(DB1, INPUT);
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pinMode(DB2, INPUT);
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pinMode(DB3, INPUT);
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pinMode(DB4, INPUT);
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pinMode(DB5, INPUT);
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pinMode(DB6, INPUT);
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pinMode(DB7, INPUT);
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digitalWrite(DB0, LOW);
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digitalWrite(DB1, LOW);
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digitalWrite(DB2, LOW);
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digitalWrite(DB3, LOW);
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digitalWrite(DB4, LOW);
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digitalWrite(DB5, LOW);
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digitalWrite(DB6, LOW);
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digitalWrite(DB7, LOW);
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// Detect if the data bus is tri-stated
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delay(1);
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int test0 = analogRead(DB0);
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// These numbers might need to be adjusted for each Arduino board
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dbTristated = test0>HI_Z_LOW && test0
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byte d0 = digitalRead(DB0);
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byte d1 = digitalRead(DB1);
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byte d2 = digitalRead(DB2);
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byte d3 = digitalRead(DB3);
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byte d4 = digitalRead(DB4);
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byte d5 = digitalRead(DB5);
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byte d6 = digitalRead(DB6);
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byte d7 = digitalRead(DB7);
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db = (d7<<7)|(d6<<6)|(d5<<5)|(d4<<4)|(d3<<3)|(d2<<2)|(d1<<1)|d0;
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}
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// Read a value of Z80 address bus and store it into the ab variable.
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// In addition, try to detect when a bus is tri-stated and write 0xFFF if so.
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void GetAddressFromAB()
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{
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// Detect if the address bus is tri-stated
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int test0 = analogRead(A0);
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// These numbers might need to be adjusted for each Arduino board
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abTristated = test0>HI_Z_LOW && test0
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int a0 = digitalRead(A0);
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int a1 = digitalRead(A1);
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int a2 = digitalRead(A2);
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int a3 = digitalRead(A3);
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int a4 = digitalRead(A4);
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int a5 = digitalRead(A5);
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int a6 = digitalRead(A6);
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int a7 = digitalRead(A7);
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ab = (a7<<7)|(a6<<6)|(a5<<5)|(a4<<4)|(a3<<3)|(a2<<2)|(a1<<1)|a0;
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}
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311 |
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// Read all control pins on the Z80 and store them into internal variables
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312 |
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void ReadControlState()
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313 |
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{
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314 |
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halt = digitalRead(HALT);
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315 |
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mreq = digitalRead(MREQ);
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316 |
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iorq = digitalRead(IORQ);
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rfsh = digitalRead(RFSH);
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m1 = digitalRead(M1);
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busak = digitalRead(BUSAK);
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320 |
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wr = digitalRead(WR);
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rd = digitalRead(RD);
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}
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// Dump the Z80 state as stored in internal variables
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325 |
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void DumpState(bool suppress)
|
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{
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327 |
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if (!suppress)
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{
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329 |
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// Select your character for tri-stated bus
|
330 |
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char abStr[4] = { "---" };
|
331 |
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char dbStr[3] = { "--" };
|
332 |
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if (!abTristated) sprintf(abStr, "%03X", ab);
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if (!dbTristated) sprintf(dbStr, "%02X", db);
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if (T==1 && clkCountHi)
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p("-----------------------------------------------------------+\r\n");
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p("#%03d%c T%-2d AB:%s DB:%s %s %s %s %s %s %s %s %s |%s%s%s%s %s\r\n",
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clkCount<0? 0 : clkCount, clkCountHi ? 'H' : 'L', T,
|
338 |
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abStr, dbStr,
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m1?" ":"M1", rfsh?" ":"RFSH", mreq?" ":"MREQ", rd?" ":"RD", wr?" ":"WR", iorq?" ":"IORQ", busak?" ":"BUSAK",halt?" ":"HALT",
|
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zint?"":"[INT]", nmi?"":"[NMI]", busrq?"":"[BUSRQ]", wait?"":"[WAIT]",
|
341 |
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extraInfo);
|
342 |
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}
|
343 |
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extraInfo[0] = 0;
|
344 |
|
|
}
|
345 |
|
|
|
346 |
|
|
// -----------------------------------------------------------
|
347 |
|
|
// Main loop routine runs over and over again forever
|
348 |
|
|
// -----------------------------------------------------------
|
349 |
|
|
void loop()
|
350 |
|
|
{
|
351 |
|
|
//--------------------------------------------------------
|
352 |
|
|
// Clock goes high
|
353 |
|
|
//--------------------------------------------------------
|
354 |
|
|
delay(1); digitalWrite(CLK, HIGH); delay(1);
|
355 |
|
|
|
356 |
|
|
clkCountHi = 1;
|
357 |
|
|
clkCount++;
|
358 |
|
|
T++;
|
359 |
|
|
tracePauseCount++;
|
360 |
|
|
ReadControlState();
|
361 |
|
|
GetAddressFromAB();
|
362 |
|
|
if (Mlast==1 && m1==0)
|
363 |
|
|
T = 1, m1Count++;
|
364 |
|
|
Mlast = m1;
|
365 |
|
|
bool suppressDump = false;
|
366 |
|
|
if (!traceRefresh & !rfsh) suppressDump = true;
|
367 |
|
|
|
368 |
|
|
// If the number of M1 cycles has been reached, skip the rest since we dont
|
369 |
|
|
// want to execute this M1 phase
|
370 |
|
|
if (m1Count==stopAtM1)
|
371 |
|
|
{
|
372 |
|
|
sprintf(extraInfo, "Number of M1 cycles reached"), running = false;
|
373 |
|
|
p("-----------------------------------------------------------+\r\n");
|
374 |
|
|
goto control;
|
375 |
|
|
}
|
376 |
|
|
|
377 |
|
|
// If the address is tri-stated, skip checking various combinations of
|
378 |
|
|
// control signals since they may also be floating and we can't detect that
|
379 |
|
|
if (!abTristated)
|
380 |
|
|
{
|
381 |
|
|
// Simulate read from RAM
|
382 |
|
|
if (!mreq && !rd)
|
383 |
|
|
{
|
384 |
|
|
SetDataToDB(ram[ab & 0xFF]);
|
385 |
|
|
if (!m1)
|
386 |
|
|
sprintf(extraInfo, "Opcode read from %03X -> %02X", ab, ram[ab & 0xFF]);
|
387 |
|
|
else
|
388 |
|
|
sprintf(extraInfo, "Memory read from %03X -> %02X", ab, ram[ab & 0xFF]);
|
389 |
|
|
}
|
390 |
|
|
else
|
391 |
|
|
// Simulate interrupt requesting a vector
|
392 |
|
|
if (!m1 && !iorq)
|
393 |
|
|
{
|
394 |
|
|
SetDataToDB(iorqVector);
|
395 |
|
|
sprintf(extraInfo, "Pushing vector %02X", iorqVector);
|
396 |
|
|
}
|
397 |
|
|
else
|
398 |
|
|
GetDataFromDB();
|
399 |
|
|
|
400 |
|
|
// Simulate write to RAM
|
401 |
|
|
if (!mreq && !wr)
|
402 |
|
|
{
|
403 |
|
|
ram[ab & 0xFF] = db;
|
404 |
|
|
sprintf(extraInfo, "Memory write to %03X <- %02X", ab, db);
|
405 |
|
|
}
|
406 |
|
|
|
407 |
|
|
// Detect I/O read: We don't place anything on the bus
|
408 |
|
|
if (!iorq && !rd)
|
409 |
|
|
{
|
410 |
|
|
sprintf(extraInfo, "I/O read from %03X", ab);
|
411 |
|
|
}
|
412 |
|
|
|
413 |
|
|
// Detect I/O write
|
414 |
|
|
if (!iorq && !wr)
|
415 |
|
|
{
|
416 |
|
|
sprintf(extraInfo, "I/O write to %03X <- %02X", ab, db);
|
417 |
|
|
}
|
418 |
|
|
|
419 |
|
|
// Capture memory refresh cycle
|
420 |
|
|
if (!mreq && !rfsh)
|
421 |
|
|
{
|
422 |
|
|
sprintf(extraInfo, "Refresh address %03X", ab);
|
423 |
|
|
}
|
424 |
|
|
}
|
425 |
|
|
else
|
426 |
|
|
GetDataFromDB();
|
427 |
|
|
|
428 |
|
|
DumpState(suppressDump);
|
429 |
|
|
|
430 |
|
|
// If the user wanted to pause simulation after a certain number of
|
431 |
|
|
// clocks, handle it here. If the key pressed to continue was not Enter,
|
432 |
|
|
// stop the simulation to issue that command
|
433 |
|
|
if (tracePause==tracePauseCount)
|
434 |
|
|
{
|
435 |
|
|
while(Serial.available()==0) ;
|
436 |
|
|
if (Serial.peek()!='\r')
|
437 |
|
|
sprintf(extraInfo, "Continue keypress was not Enter"), running = false;
|
438 |
|
|
else
|
439 |
|
|
Serial.read();
|
440 |
|
|
tracePauseCount = 0;
|
441 |
|
|
}
|
442 |
|
|
|
443 |
|
|
//--------------------------------------------------------
|
444 |
|
|
// Clock goes low
|
445 |
|
|
//--------------------------------------------------------
|
446 |
|
|
delay(1); digitalWrite(CLK, LOW); delay(1);
|
447 |
|
|
|
448 |
|
|
clkCountHi = 0;
|
449 |
|
|
if (traceShowBothPhases)
|
450 |
|
|
{
|
451 |
|
|
ReadControlState();
|
452 |
|
|
GetAddressFromAB();
|
453 |
|
|
DumpState(suppressDump);
|
454 |
|
|
}
|
455 |
|
|
|
456 |
|
|
// Perform various actions at the requested clock number
|
457 |
|
|
// if the count is positive (we start it at -2 to skip initial 2T)
|
458 |
|
|
if (clkCount>=0)
|
459 |
|
|
{
|
460 |
|
|
if (clkCount==intAtClk) zint = 0;
|
461 |
|
|
if (clkCount==nmiAtClk) nmi = 0;
|
462 |
|
|
if (clkCount==busrqAtClk) busrq = 0;
|
463 |
|
|
if (clkCount==resetAtClk) reset = 0;
|
464 |
|
|
if (clkCount==waitAtClk) wait = 0;
|
465 |
|
|
// De-assert all control pins at this clock number
|
466 |
|
|
if (clkCount==clearAtClk)
|
467 |
|
|
zint = nmi = busrq = reset = wait = 1;
|
468 |
|
|
WriteControlPins();
|
469 |
|
|
|
470 |
|
|
// Stop the simulation under some conditions
|
471 |
|
|
if (clkCount==stopAtClk)
|
472 |
|
|
sprintf(extraInfo, "Number of clocks reached"), running = false;
|
473 |
|
|
if (stopAtHalt&!halt)
|
474 |
|
|
sprintf(extraInfo, "HALT instruction"), running = false;
|
475 |
|
|
}
|
476 |
|
|
|
477 |
|
|
//--------------------------------------------------------
|
478 |
|
|
// Trace/simulation control handler
|
479 |
|
|
//--------------------------------------------------------
|
480 |
|
|
control:
|
481 |
|
|
if (!running)
|
482 |
|
|
{
|
483 |
|
|
p(":Simulation stopped: %s\r\n", extraInfo);
|
484 |
|
|
extraInfo[0] = 0;
|
485 |
|
|
digitalWrite(CLK, HIGH);
|
486 |
|
|
zint = nmi = busrq = wait = 1;
|
487 |
|
|
WriteControlPins();
|
488 |
|
|
|
489 |
|
|
while(!running)
|
490 |
|
|
{
|
491 |
|
|
// Expect a command from the serial port
|
492 |
|
|
if (Serial.available()>0)
|
493 |
|
|
{
|
494 |
|
|
memset(temp, 0, TEMP_SIZE);
|
495 |
|
|
Serial.readBytesUntil('\r', temp, TEMP_SIZE-1);
|
496 |
|
|
|
497 |
|
|
// Option ":" : this is not really a user option. This is used to
|
498 |
|
|
// Intel HEX format values into the RAM buffer
|
499 |
|
|
// Multiple lines may be pasted. They are separated by a space character.
|
500 |
|
|
char *pTemp = temp;
|
501 |
|
|
while (*pTemp==':')
|
502 |
|
|
{
|
503 |
|
|
byte bytes = hexFromTemp(pTemp, 0);
|
504 |
|
|
if (bytes>0)
|
505 |
|
|
{
|
506 |
|
|
int address = (hexFromTemp(pTemp, 1)<<8) + hexFromTemp(pTemp, 2);
|
507 |
|
|
byte recordType = hexFromTemp(pTemp, 3);
|
508 |
|
|
p("%04X:", address);
|
509 |
|
|
for (int i=0; i
|
510 |
|
|
{
|
511 |
|
|
ram[(address + i) & 0xFF] = hexFromTemp(pTemp, 4+i);
|
512 |
|
|
p(" %02X", hexFromTemp(pTemp, 4+i));
|
513 |
|
|
}
|
514 |
|
|
p("\r\n");
|
515 |
|
|
}
|
516 |
|
|
pTemp += bytes*2 + 12; // Skip to the next possible line of hex entry
|
517 |
|
|
}
|
518 |
|
|
// Option "r" : reset and run the simulation
|
519 |
|
|
if (temp[0]=='r')
|
520 |
|
|
{
|
521 |
|
|
// If the variable 9 (Issue RESET) is not set, perform a RESET and run the simulation.
|
522 |
|
|
// If the variable was set, skip reset sequence since we might be testing it.
|
523 |
|
|
if (resetAtClk<0)
|
524 |
|
|
DoReset();
|
525 |
|
|
running = true;
|
526 |
|
|
}
|
527 |
|
|
// Option "sc" : clear simulation variables to their default values
|
528 |
|
|
if (temp[0]=='s' && temp[1]=='c')
|
529 |
|
|
{
|
530 |
|
|
ResetSimulationVars();
|
531 |
|
|
temp[1] = 0; // Proceed to dump all variables...
|
532 |
|
|
}
|
533 |
|
|
// Option "s" : show and set internal control variables
|
534 |
|
|
if (temp[0]=='s' && temp[1]!='c')
|
535 |
|
|
{
|
536 |
|
|
// Show or set the simulation parameters
|
537 |
|
|
int var = 0, value;
|
538 |
|
|
int args = sscanf(&temp[1], "%d %d\r\n", &var, &value);
|
539 |
|
|
// Parameter for the option #12 is read in as a hex; others are decimal by default
|
540 |
|
|
if (var==12)
|
541 |
|
|
args = sscanf(&temp[1], "%d %x\r\n", &var, &value);
|
542 |
|
|
if (args==2)
|
543 |
|
|
{
|
544 |
|
|
if (var==0) traceShowBothPhases = value;
|
545 |
|
|
if (var==1) traceRefresh = value;
|
546 |
|
|
if (var==2) tracePause = value;
|
547 |
|
|
if (var==3) stopAtClk = value;
|
548 |
|
|
if (var==4) stopAtM1 = value;
|
549 |
|
|
if (var==5) stopAtHalt = value;
|
550 |
|
|
if (var==6) intAtClk = value;
|
551 |
|
|
if (var==7) nmiAtClk = value;
|
552 |
|
|
if (var==8) busrqAtClk = value;
|
553 |
|
|
if (var==9) resetAtClk = value;
|
554 |
|
|
if (var==10) waitAtClk = value;
|
555 |
|
|
if (var==11) clearAtClk = value;
|
556 |
|
|
if (var==12) iorqVector = value & 0xFF;
|
557 |
|
|
}
|
558 |
|
|
p("------ Simulation variables ------\r\n");
|
559 |
|
|
p("#0 Trace both clock phases = %d\r\n", traceShowBothPhases);
|
560 |
|
|
p("#1 Trace refresh cycles = %d\r\n", traceRefresh);
|
561 |
|
|
p("#2 Pause for keypress every = %d\r\n", tracePause);
|
562 |
|
|
p("#3 Stop after clock # = %d\r\n", stopAtClk);
|
563 |
|
|
p("#4 Stop after # M1 cycles = %d\r\n", stopAtM1);
|
564 |
|
|
p("#5 Stop at HALT = %d\r\n", stopAtHalt);
|
565 |
|
|
p("#6 Issue INT at clock # = %d\r\n", intAtClk);
|
566 |
|
|
p("#7 Issue NMI at clock # = %d\r\n", nmiAtClk);
|
567 |
|
|
p("#8 Issue BUSRQ at clock # = %d\r\n", busrqAtClk);
|
568 |
|
|
p("#9 Issue RESET at clock # = %d\r\n", resetAtClk);
|
569 |
|
|
p("#10 Issue WAIT at clock # = %d\r\n", waitAtClk);
|
570 |
|
|
p("#11 Clear all at clock # = %d\r\n", clearAtClk);
|
571 |
|
|
p("#12 Push IORQ vector #(hex) = %2X\r\n", iorqVector);
|
572 |
|
|
}
|
573 |
|
|
// Option "m" : dump RAM memory
|
574 |
|
|
if (temp[0]=='m' && temp[1]!='c')
|
575 |
|
|
{
|
576 |
|
|
// Dump the content of a RAM buffer
|
577 |
|
|
p(" 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F\r\n");
|
578 |
|
|
p(" +-----------------------------------------------\r\n");
|
579 |
|
|
for(int i=0; i<16; i++)
|
580 |
|
|
{
|
581 |
|
|
p("%02X |", i);
|
582 |
|
|
for(int j=0; j<16; j++)
|
583 |
|
|
{
|
584 |
|
|
p("%02X ", ram[i*16+j]);
|
585 |
|
|
}
|
586 |
|
|
p("\r\n");
|
587 |
|
|
}
|
588 |
|
|
}
|
589 |
|
|
// Option "mc" : clear RAM memory
|
590 |
|
|
if (temp[0]=='m' && temp[1]=='c')
|
591 |
|
|
{
|
592 |
|
|
memset(ram, 0, sizeof(ram));
|
593 |
|
|
p("RAM cleared\r\n");
|
594 |
|
|
}
|
595 |
|
|
// Option "?" : print help
|
596 |
|
|
if (temp[0]=='?' || temp[0]=='h')
|
597 |
|
|
{
|
598 |
|
|
p("s - show simulation variables\r\n");
|
599 |
|
|
p("s #var value - set simulation variable number to a value\r\n");
|
600 |
|
|
p("sc - clear simulation variables to their default values\r\n");
|
601 |
|
|
p("r - restart the simulation\r\n");
|
602 |
|
|
p(":INTEL-HEX - reload RAM buffer with a given data stream\r\n");
|
603 |
|
|
p("m - dump the content of the RAM buffer\r\n");
|
604 |
|
|
p("mc - clear the RAM buffer\r\n");
|
605 |
|
|
}
|
606 |
|
|
}
|
607 |
|
|
}
|
608 |
|
|
}
|
609 |
|
|
}
|