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[/] [aes-128_pipelined_encryption/] [tags/] [R0/] [syn/] [setup.tcl] - Blame information for rev 2

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1 2 Amr_Salah
# 
2
# Project automation script for AES 
3
# 
4
# Created for ISE version 12.1
5
# 
6
# This file contains several Tcl procedures (procs) that you can use to automate
7
# your project by running from xtclsh or the Project Navigator Tcl console.
8
# If you load this file (using the Tcl command: source AES.tcl), then you can
9
# run any of the procs included here.
10
# 
11
# This script is generated assuming your project has HDL sources.
12
# Several of the defined procs won't apply to an EDIF or NGC based project.
13
# If that is the case, simply remove them from this script.
14
# 
15
# You may also edit any of these procs to customize them. See comments in each
16
# proc for more instructions.
17
# 
18
# This file contains the following procedures:
19
# 
20
# Top Level procs (meant to be called directly by the user):
21
#    run_process: you can use this top-level procedure to run any processes
22
#        that you choose to by adding and removing comments, or by
23
#        adding new entries.
24
#    rebuild_project: you can alternatively use this top-level procedure
25
#        to recreate your entire project, and the run selected processes.
26
# 
27
# Lower Level (helper) procs (called under in various cases by the top level procs):
28
#    show_help: print some basic information describing how this script works
29
#    add_source_files: adds the listed source files to your project.
30
#    set_project_props: sets the project properties that were in effect when this
31
#        script was generated.
32
#    create_libraries: creates and adds file to VHDL libraries that were defined when
33
#        this script was generated.
34
#    set_process_props: set the process properties as they were set for your project
35
#        when this script was generated.
36
# 
37
 
38
set myProject "AES"
39
set myScript "setup.tcl"
40
 
41
# 
42
# Main (top-level) routines
43
# 
44
 
45
# 
46
# run_process
47
# This procedure is used to run processes on an existing project. You may comment or
48
# uncomment lines to control which processes are run. This routine is set up to run
49
# the Implement Design and Generate Programming File processes by default. This proc
50
# also sets process properties as specified in the "set_process_props" proc. Only
51
# those properties which have values different from their current settings in the project
52
# file will be modified in the project.
53
# 
54
proc run_process {} {
55
 
56
   global myScript
57
   global myProject
58
 
59
   ## put out a 'heartbeat' - so we know something's happening.
60
   puts "\n$myScript: running ($myProject)...\n"
61
 
62
   if { ! [ open_project ] } {
63
      return false
64
   }
65
 
66
   set_process_props
67
   #
68
   # Remove the comment characters (#'s) to enable the following commands 
69
   process run "Synthesize"
70
   process run "Translate"
71
   process run "Map"
72
   process run "Place & Route"
73
   process run "Generate Post-Place & Route Simulation Model"
74
   #
75
   puts "Running 'Implement Design'"
76
   if { ! [ process run "Implement Design" ] } {
77
      puts "$myScript: Implementation run failed, check run output for details."
78
      project close
79
      return
80
   }
81
   puts "Running 'Generate Programming File'"
82
   if { ! [ process run "Generate Programming File" ] } {
83
      puts "$myScript: Generate Programming File run failed, check run output for details."
84
      project close
85
      return
86
   }
87
 
88
   puts "Run completed."
89
   project close
90
 
91
}
92
 
93
# 
94
# rebuild_project
95
# 
96
# This procedure renames the project file (if it exists) and recreates the project.
97
# It then sets project properties and adds project sources as specified by the
98
# set_project_props and add_source_files support procs. It recreates VHDL libraries
99
# and partitions as they existed at the time this script was generated.
100
# 
101
# It then calls run_process to set process properties and run selected processes.
102
# 
103
proc rebuild_project {} {
104
 
105
   global myScript
106
   global myProject
107
 
108
   project close
109
   ## put out a 'heartbeat' - so we know something's happening.
110
   puts "\n$myScript: Rebuilding ($myProject)...\n"
111
 
112
   set proj_exts [ list ise xise gise ]
113
   foreach ext $proj_exts {
114
      set proj_name "${myProject}.$ext"
115
      if { [ file exists $proj_name ] } {
116
         file delete $proj_name
117
      }
118
   }
119
 
120
   project new $myProject
121
   set_project_props
122
   add_source_files
123
   create_libraries
124
   puts "$myScript: project rebuild completed."
125
 
126
   run_process
127
 
128
}
129
 
130
# 
131
# Support Routines
132
# 
133
 
134
# 
135
# show_help: print information to help users understand the options available when
136
#            running this script.
137
# 
138
proc show_help {} {
139
 
140
   global myScript
141
 
142
   puts ""
143
   puts "usage: xtclsh $myScript <options>"
144
   puts "       or you can run xtclsh and then enter 'source $myScript'."
145
   puts ""
146
   puts "options:"
147
   puts "   run_process       - set properties and run processes."
148
   puts "   rebuild_project   - rebuild the project from scratch and run processes."
149
   puts "   set_project_props - set project properties (device, speed, etc.)"
150
   puts "   add_source_files  - add source files"
151
   puts "   create_libraries  - create vhdl libraries"
152
   puts "   set_process_props - set process property values"
153
   puts "   show_help         - print this message"
154
   puts ""
155
}
156
 
157
proc open_project {} {
158
 
159
   global myScript
160
   global myProject
161
 
162
   if { ! [ file exists ${myProject}.xise ] } {
163
      ## project file isn't there, rebuild it.
164
      puts "Project $myProject not found. Use project_rebuild to recreate it."
165
      return false
166
   }
167
 
168
   project open $myProject
169
 
170
   return true
171
 
172
}
173
# 
174
# set_project_props
175
# 
176
# This procedure sets the project properties as they were set in the project
177
# at the time this script was generated.
178
# 
179
proc set_project_props {} {
180
 
181
   global myScript
182
 
183
   if { ! [ open_project ] } {
184
      return false
185
   }
186
 
187
   puts "$myScript: Setting project properties..."
188
 
189
   project set family "Virtex6"
190
   project set device "xc6vcx240t"
191
   project set package "ff784"
192
   project set speed "-2"
193
   project set top_level_module_type "HDL"
194
   project set synthesis_tool "XST (VHDL/Verilog)"
195
   project set simulator "Modelsim-SE Verilog"
196
   project set "Preferred Language" "Verilog"
197
   project set "Enable Message Filtering" "false"
198
 
199
}
200
 
201
 
202
# 
203
# add_source_files
204
# 
205
# This procedure add the source files that were known to the project at the
206
# time this script was generated.
207
# 
208
proc add_source_files {} {
209
 
210
   global myScript
211
 
212
   if { ! [ open_project ] } {
213
      return false
214
   }
215
 
216
   puts "$myScript: Adding sources to project..."
217
 
218
   xfile add "../rtl/AddRoundKey.v"
219
   xfile add "../rtl/KeyExpantion.v"
220
   xfile add "../rtl/MixColumns.v"
221
   xfile add "../rtl/Round.v"
222
   xfile add "../rtl/RoundKeyGen.v"
223
   xfile add "../rtl/SBox.v"
224
   xfile add "../rtl/ShiftRows.v"
225
   xfile add "../rtl/SubBytes.v"
226
   xfile add "../rtl/Top_PipelinedCipher.v"
227
   xfile add "./Top_PipelinedCipher.ucf"
228
 
229
   # Set the Top Module as well...
230
   project set top "Top_PipelinedCipher"
231
 
232
   puts "$myScript: project sources reloaded."
233
 
234
} ; # end add_source_files
235
 
236
# 
237
# create_libraries
238
# 
239
# This procedure defines VHDL libraries and associates files with those libraries.
240
# It is expected to be used when recreating the project. Any libraries defined
241
# when this script was generated are recreated by this procedure.
242
# 
243
proc create_libraries {} {
244
 
245
   global myScript
246
 
247
   if { ! [ open_project ] } {
248
      return false
249
   }
250
 
251
   puts "$myScript: Creating libraries..."
252
 
253
 
254
   # must close the project or library definitions aren't saved.
255
   project save
256
 
257
} ; # end create_libraries
258
 
259
# 
260
# set_process_props
261
# 
262
# This procedure sets properties as requested during script generation (either
263
# all of the properties, or only those modified from their defaults).
264
# 
265
proc set_process_props {} {
266
 
267
   global myScript
268
 
269
   if { ! [ open_project ] } {
270
      return false
271
   }
272
 
273
   puts "$myScript: setting process properties..."
274
 
275
   project set "Compiled Library Directory" "\$XILINX/<language>/<simulator>"
276
   project set "Global Optimization" "Off" -process "Map"
277
   project set "Use DSP Block" "Auto" -process "Synthesize - XST"
278
   project set "Enable Cyclic Redundancy Checking (CRC)" "true" -process "Generate Programming File"
279
   project set "Configuration Rate" "2" -process "Generate Programming File"
280
   project set "Pack I/O Registers/Latches into IOBs" "Off" -process "Map"
281
   project set "Place And Route Mode" "Route Only" -process "Place & Route"
282
   project set "Number of Clock Buffers" "32" -process "Synthesize - XST"
283
   project set "Max Fanout" "100000" -process "Synthesize - XST"
284
   project set "Use Clock Enable" "Auto" -process "Synthesize - XST"
285
   project set "Use Synchronous Reset" "Auto" -process "Synthesize - XST"
286
   project set "Use Synchronous Set" "Auto" -process "Synthesize - XST"
287
   project set "Enable Hardware Co-Simulation" "false"
288
   project set "Filter Files From Compile Order" "true"
289
   #project set "Use Custom Project File" "false" -process "Post-Map Check Syntax"
290
   #project set "Use Custom Project File" "false" -process "Post-Place & Route Check Syntax"
291
   #project set "Use Custom Project File" "false" -process "Post-Translate Check Syntax"
292
   project set "Last Applied Goal" "Balanced"
293
   project set "Last Applied Strategy" "Xilinx Default (unlocked)"
294
   project set "Last Unlock Status" "false"
295
   project set "Manual Compile Order" "false"
296
   project set "Placer Effort Level" "High" -process "Map"
297
   project set "Extra Cost Tables" "0" -process "Map"
298
   project set "LUT Combining" "Off" -process "Map"
299
   project set "Combinatorial Logic Optimization" "false" -process "Map"
300
   project set "Starting Placer Cost Table (1-100)" "1" -process "Map"
301
   project set "Power Reduction" "Off" -process "Map"
302
   project set "Register Duplication" "Off" -process "Map"
303
   project set "Project Generator" "ProjNav"
304
   project set "Property Specification in Project File" "Store all values"
305
   project set "Reduce Control Sets" "Auto" -process "Synthesize - XST"
306
   project set "Selected Module Instance Name" "/Top_PipelinedCipher_tb"
307
   project set "Shift Register Minimum Size" "2" -process "Synthesize - XST"
308
   project set "Case Implementation Style" "None" -process "Synthesize - XST"
309
   project set "Mux Extraction" "Yes"
310
   project set "RAM Extraction" "true" -process "Synthesize - XST"
311
   project set "ROM Extraction" "true" -process "Synthesize - XST"
312
   project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
313
   project set "Optimization Goal" "Speed" -process "Synthesize - XST"
314
   project set "Optimization Effort" "Normal" -process "Synthesize - XST"
315
   project set "Resource Sharing" "true" -process "Synthesize - XST"
316
   project set "Shift Register Extraction" "true" -process "Synthesize - XST"
317
   project set "User Browsed Strategy Files" ""
318
   project set "VHDL Source Analysis Standard" "VHDL-93"
319
   project set "Working Directory" "."
320
   project set "JTAG to System Monitor Connection" "Enable" -process "Generate Programming File"
321
   project set "Other Bitgen Command Line Options" "" -process "Generate Programming File"
322
   project set "Generate Detailed Package Parasitics" "false" -process "Generate IBIS Model"
323
   project set "Maximum Signal Name Length" "20" -process "Generate IBIS Model"
324
   project set "Show All Models" "false" -process "Generate IBIS Model"
325
   project set "Target UCF File Name" "" -process "Back-annotate Pin Locations"
326
   project set "Ignore User Timing Constraints" "false" -process "Map"
327
   project set "Use RLOC Constraints" "Yes" -process "Map"
328
   project set "Other Map Command Line Options" "" -process "Map"
329
   project set "Use LOC Constraints" "true" -process "Translate"
330
   project set "Other Ngdbuild Command Line Options" "" -process "Translate"
331
   project set "Ignore User Timing Constraints" "false" -process "Place & Route"
332
   project set "Other Place & Route Command Line Options" "" -process "Place & Route"
333
   project set "BPI Reads Per Page" "1" -process "Generate Programming File"
334
   project set "Configuration Pin Busy" "Pull Up" -process "Generate Programming File"
335
   project set "Configuration Clk (Configuration Pins)" "Pull Up" -process "Generate Programming File"
336
   project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
337
   project set "Configuration Pin CS" "Pull Up" -process "Generate Programming File"
338
   project set "DCI Update Mode" "As Required" -process "Generate Programming File"
339
   project set "Configuration Pin DIn" "Pull Up" -process "Generate Programming File"
340
   project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
341
   project set "Create ASCII Configuration File" "false" -process "Generate Programming File"
342
   project set "Create Binary Configuration File" "false" -process "Generate Programming File"
343
   project set "Create Bit File" "true" -process "Generate Programming File"
344
   project set "Enable BitStream Compression" "false" -process "Generate Programming File"
345
   project set "Run Design Rules Checker (DRC)" "true" -process "Generate Programming File"
346
   project set "Create IEEE 1532 Configuration File" "false" -process "Generate Programming File"
347
   project set "Create ReadBack Data Files" "false" -process "Generate Programming File"
348
   project set "Configuration Pin HSWAPEN" "Pull Up" -process "Generate Programming File"
349
   project set "Configuration Pin Init" "Pull Up" -process "Generate Programming File"
350
   project set "Configuration Pin M0" "Pull Up" -process "Generate Programming File"
351
   project set "Configuration Pin M1" "Pull Up" -process "Generate Programming File"
352
   project set "Configuration Pin M2" "Pull Up" -process "Generate Programming File"
353
   project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
354
   project set "Power Down Device if Over Safe Temperature" "false" -process "Generate Programming File"
355
   project set "Configuration Pin RdWr" "Pull Up" -process "Generate Programming File"
356
   project set "Starting Address for Fallback Configuration" "0x00000000" -process "Generate Programming File"
357
   project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
358
   project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
359
   project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
360
   project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
361
   project set "Unused IOB Pins" "Pull Down" -process "Generate Programming File"
362
   project set "Watchdog Timer Mode" "Off" -process "Generate Programming File"
363
   project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
364
   project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
365
   project set "Drive Done Pin High" "false" -process "Generate Programming File"
366
   project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
367
   project set "Wait for DCI Match (Output Events)" "Auto" -process "Generate Programming File"
368
   project set "Wait for PLL Lock (Output Events)" "No Wait" -process "Generate Programming File"
369
   project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
370
   project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
371
   project set "Enable Internal Done Pipe" "false" -process "Generate Programming File"
372
   project set "Allow Logic Optimization Across Hierarchy" "false" -process "Map"
373
   project set "Maximum Compression" "false" -process "Map"
374
   project set "Generate Detailed MAP Report" "false" -process "Map"
375
   project set "Map Slice Logic into Unused Block RAMs" "false" -process "Map"
376
   project set "Perform Timing-Driven Packing and Placement" "false"
377
   project set "Trim Unconnected Signals" "true" -process "Map"
378
   project set "Create I/O Pads from Ports" "false" -process "Translate"
379
   project set "Macro Search Path" "" -process "Translate"
380
   project set "Netlist Translation Type" "Timestamp" -process "Translate"
381
   project set "User Rules File for Netlister Launcher" "" -process "Translate"
382
   project set "Allow Unexpanded Blocks" "false" -process "Translate"
383
   project set "Allow Unmatched LOC Constraints" "false" -process "Translate"
384
   project set "Allow Unmatched Timing Group Constraints" "false" -process "Translate"
385
   project set "Add I/O Buffers" "true" -process "Synthesize - XST"
386
   project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
387
   project set "Keep Hierarchy" "No" -process "Synthesize - XST"
388
   project set "Register Balancing" "No" -process "Synthesize - XST"
389
   project set "Register Duplication" "true" -process "Synthesize - XST"
390
   project set "Asynchronous To Synchronous" "false" -process "Synthesize - XST"
391
   project set "Automatic BRAM Packing" "false" -process "Synthesize - XST"
392
   project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
393
   project set "Bus Delimiter" "<>" -process "Synthesize - XST"
394
   project set "Case" "Maintain" -process "Synthesize - XST"
395
   project set "Cores Search Directories" "" -process "Synthesize - XST"
396
   project set "Cross Clock Analysis" "false" -process "Synthesize - XST"
397
   project set "DSP Utilization Ratio" "100" -process "Synthesize - XST"
398
   project set "Equivalent Register Removal" "true" -process "Synthesize - XST"
399
   project set "FSM Style" "LUT" -process "Synthesize - XST"
400
   project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
401
   project set "Generics, Parameters" "" -process "Synthesize - XST"
402
   project set "Hierarchy Separator" "/" -process "Synthesize - XST"
403
   project set "HDL INI File" "" -process "Synthesize - XST"
404
   project set "LUT Combining" "Auto" -process "Synthesize - XST"
405
   project set "Library Search Order" "" -process "Synthesize - XST"
406
   project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
407
   project set "Optimize Instantiated Primitives" "false" -process "Synthesize - XST"
408
   project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
409
   project set "Power Reduction" "false" -process "Synthesize - XST"
410
   project set "Read Cores" "true" -process "Synthesize - XST"
411
   project set "LUT-FF Pairs Utilization Ratio" "100" -process "Synthesize - XST"
412
   project set "Use Synthesis Constraints File" "true" -process "Synthesize - XST"
413
   project set "Verilog Include Directories" "" -process "Synthesize - XST"
414
   project set "Verilog 2001" "true"
415
   project set "Verilog Macros" "" -process "Synthesize - XST"
416
   project set "Write Timing Constraints" "false" -process "Synthesize - XST"
417
   project set "Other XST Command Line Options" "" -process "Synthesize - XST"
418
   project set "Timing Mode" "Performance Evaluation" -process "Map"
419
   project set "Generate Asynchronous Delay Report" "false" -process "Place & Route"
420
   project set "Generate Clock Region Report" "false" -process "Place & Route"
421
   project set "Generate Post-Place & Route Power Report" "false" -process "Place & Route"
422
   project set "Generate Post-Place & Route Simulation Model" "false" -process "Place & Route"
423
   project set "Power Reduction" "false" -process "Place & Route"
424
   project set "Place & Route Effort Level (Overall)" "High" -process "Place & Route"
425
   project set "Auto Implementation Compile Order" "true"
426
   project set "Auto Implementation Top" "false"
427
   project set "Equivalent Register Removal" "true" -process "Map"
428
   project set "Placer Extra Effort" "None" -process "Map"
429
   project set "Power Activity File" "" -process "Map"
430
   project set "Retiming" "false" -process "Map"
431
   project set "Synthesis Constraints File" "" -process "Synthesize - XST"
432
   project set "RAM Style" "Auto" -process "Synthesize - XST"
433
   project set "Verbose Property Persistence" "true"
434
   project set "Encrypt Bitstream" "false" -process "Generate Programming File"
435
   project set "Output File Name" "Top_PipelinedCipher" -process "Generate IBIS Model"
436
   project set "Enable Multi-Threading" "Off" -process "Place & Route"
437
   project set "Timing Mode" "Performance Evaluation" -process "Place & Route"
438
   project set "Cycles for First BPI Page Read" "1" -process "Generate Programming File"
439
   project set "Enable Debugging of Serial Mode BitStream" "false" -process "Generate Programming File"
440
   project set "Create Logic Allocation File" "false" -process "Generate Programming File"
441
   project set "Create Mask File" "false" -process "Generate Programming File"
442
   project set "Watchdog Timer Value" "0x000000" -process "Generate Programming File"
443
   project set "Allow SelectMAP Pins to Persist" "false" -process "Generate Programming File"
444
   project set "Enable Multi-Threading" "Off" -process "Map"
445
   project set "Move First Flip-Flop Stage" "true" -process "Synthesize - XST"
446
   project set "Move Last Flip-Flop Stage" "true" -process "Synthesize - XST"
447
   project set "ROM Style" "Auto" -process "Synthesize - XST"
448
   project set "Safe Implementation" "No" -process "Synthesize - XST"
449
   project set "AES Initial Vector" "" -process "Generate Programming File"
450
   project set "Power Activity File" "" -process "Place & Route"
451
   project set "Extra Effort (Highest PAR level only)" "None" -process "Place & Route"
452
   project set "HMAC Key (Hex String)" "" -process "Generate Programming File"
453
   project set "Encrypt Key Select" "BBRAM" -process "Generate Programming File"
454
   project set "AES Key (Hex String)" "" -process "Generate Programming File"
455
   project set "Input Encryption Key File" "" -process "Generate Programming File"
456
   project set "Fallback Reconfiguration" "Enable" -process "Generate Programming File"
457
   project set "Automatically Insert glbl Module in the Netlist" "true" -process "Generate Post-Place & Route Simulation Model"
458
   project set "Include SIMPRIM Models in Verilog File" "true" -process "Generate Post-Place & Route Simulation Model"
459
   project set "Include sdf_annotate task in Verilog File" "false" -process "Generate Post-Place & Route Simulation Model"
460
 
461
   puts "$myScript: project property values set."
462
 
463
} ; # end set_process_props
464
 
465
proc main {} {
466
 
467
   if { [llength $::argv] == 0 } {
468
      show_help
469
      return true
470
   }
471
 
472
   foreach option $::argv {
473
      switch $option {
474
         "show_help"           { show_help }
475
         "run_process"         { run_process }
476
         "rebuild_project"     { rebuild_project }
477
         "set_project_props"   { set_project_props }
478
         "add_source_files"    { add_source_files }
479
         "create_libraries"    { create_libraries }
480
         "set_process_props"   { set_process_props }
481
         default               { puts "unrecognized option: $option"; show_help }
482
      }
483
   }
484
}
485
 
486
if { $tcl_interactive } {
487
   show_help
488
} else {
489
   if {[catch {main} result]} {
490
      puts "$myScript failed: $result."
491
   }
492
}
493
 

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