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[/] [aes-128_pipelined_encryption/] [trunk/] [reports/] [Top_PipelinedCipher.par] - Blame information for rev 2

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Release 12.1 par M.53d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
 
AMRSALAH-PC::  Wed Jul 17 15:17:40 2013
 
par -w -intstyle ise -ol high Top_PipelinedCipher_map.ncd
Top_PipelinedCipher.ncd Top_PipelinedCipher.pcf
 
 
Constraints file: Top_PipelinedCipher.pcf.
Loading device for application Rf_Device from file '6vcx240t.nph' in environment E:\ISE12\ISE_DS\ISE.
   "Top_PipelinedCipher" is an NCD, version 3.2, device xc6vcx240t, package ff784, speed -2
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:56 - Part 'xc6vcx240t' is not a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.
 
----------------------------------------------------------------------
 
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
 
 
Device speed data version:  "PRELIMINARY 1.04 2010-04-09".
 
 
 
Device Utilization Summary:
 
Slice Logic Utilization:
  Number of Slice Registers:                10,769 out of 301,440    3%
    Number used as Flip Flops:              10,769
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                     12,475 out of 150,720    8%
    Number used as logic:                    9,842 out of 150,720    6%
      Number using O6 output only:           9,081
      Number using O5 output only:               0
      Number using O5 and O6:                  761
      Number used as ROM:                        0
    Number used as Memory:                       0 out of  58,400    0%
    Number used exclusively as route-thrus:  2,633
      Number with same-slice register load:  2,633
      Number with same-slice carry load:         0
      Number with other load:                    0
 
Slice Logic Distribution:
  Number of occupied Slices:                 3,214 out of  37,680    8%
  Number of LUT Flip Flop pairs used:       12,527
    Number with an unused Flip Flop:         5,031 out of  12,527   40%
    Number with an unused LUT:                  52 out of  12,527    1%
    Number of fully used LUT-FF pairs:       7,444 out of  12,527   59%
    Number of slice register sites lost
      to control set restrictions:               0 out of 301,440    0%
 
  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
  OVERMAPPING of BRAM resources should be ignored if the design is
  over-mapped for a non-BRAM resource or if placement fails.
 
IO Utilization:
  Number of bonded IOBs:                       389 out of     400   97%
 
Specific Feature Utilization:
  Number of RAMB36E1/FIFO36E1s:                  0 out of     416    0%
  Number of RAMB18E1/FIFO18E1s:                  0 out of     832    0%
  Number of BUFG/BUFGCTRLs:                      2 out of      32    6%
    Number used as BUFGs:                        2
    Number used as BUFGCTRLs:                    0
  Number of ILOGICE1/ISERDESE1s:                 0 out of     720    0%
  Number of OLOGICE1/OSERDESE1s:                 0 out of     720    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHCEs:                             0 out of     144    0%
  Number of BUFIODQSs:                           0 out of      72    0%
  Number of BUFRs:                               0 out of      36    0%
  Number of CAPTUREs:                            0 out of       1    0%
  Number of DSP48E1s:                            0 out of     768    0%
  Number of EFUSE_USRs:                          0 out of       1    0%
  Number of GTXE1s:                              0 out of      12    0%
  Number of IBUFDS_GTXE1s:                       0 out of       8    0%
  Number of ICAPs:                               0 out of       2    0%
  Number of IDELAYCTRLs:                         0 out of      18    0%
  Number of IODELAYE1s:                          0 out of     720    0%
  Number of MMCM_ADVs:                           0 out of      12    0%
  Number of PCIE_2_0s:                           0 out of       2    0%
  Number of STARTUPs:                            1 out of       1  100%
  Number of SYSMONs:                             0 out of       1    0%
  Number of TEMAC_SINGLEs:                       0 out of       1    0%
 
 
Overall effort level (-ol):   High
Router effort level (-rl):    High
 
Starting initial Timing Analysis.  REAL time: 35 secs
Finished initial Timing Analysis.  REAL time: 36 secs
 
Starting Router
 
 
Phase  1  : 77964 unrouted;      REAL time: 42 secs
 
Phase  2  : 70512 unrouted;      REAL time: 54 secs
 
Phase  3  : 26862 unrouted;      REAL time: 1 mins 44 secs
 
Phase  4  : 26860 unrouted; (Setup:0, Hold:1, Component Switching Limit:0)     REAL time: 1 mins 56 secs
 
Updating file: Top_PipelinedCipher.ncd with current fully routed design.
 
Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 2 mins 30 secs
 
Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 2 mins 30 secs
 
Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 2 mins 30 secs
 
Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 2 mins 30 secs
 
Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 2 mins 30 secs
 
Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 2 mins 38 secs
Total REAL time to Router completion: 2 mins 38 secs
Total CPU time to Router completion: 2 mins 42 secs
 
Partition Implementation Status
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
Generating "PAR" statistics.
 
**************************
Generating Clock Report
**************************
 
+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP | BUFGCTRL_X0Y0| No   | 3213 |  0.252     |  1.834      |
+---------------------+--------------+------+------+------------+-------------+
 
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
 
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
 
Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.
 
----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
                                            |             |    Slack   | Achievable | Errors |    Score
----------------------------------------------------------------------------------------------------------
  TS_clk = PERIOD TIMEGRP "clk" 5 ns HIGH 5 | SETUP       |     0.048ns|     4.952ns|       0|           0
  0%                                        | HOLD        |     0.006ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
 
 
All constraints were met.
 
 
Generating Pad Report.
 
All signals are completely routed.
 
Total REAL time to PAR completion: 2 mins 46 secs
Total CPU time to PAR completion: 2 mins 49 secs
 
Peak Memory Usage:  1113 MB
 
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
 
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0
 
Writing design to file Top_PipelinedCipher.ncd
 
 
 
PAR done!

Line No.	Rev	Author	Line
1	2	Amr_Salah	`Release 12.1 par M.53d (nt64)`
2			`Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.`
3
4			`AMRSALAH-PC:: Wed Jul 17 15:17:40 2013`
5
6			`par -w -intstyle ise -ol high Top_PipelinedCipher_map.ncd`
7			`Top_PipelinedCipher.ncd Top_PipelinedCipher.pcf`
8
9
10			`Constraints file: Top_PipelinedCipher.pcf.`
11			`Loading device for application Rf_Device from file '6vcx240t.nph' in environment E:\ISE12\ISE_DS\ISE.`
12			`"Top_PipelinedCipher" is an NCD, version 3.2, device xc6vcx240t, package ff784, speed -2`
13			`vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv`
14			`INFO:Security:56 - Part 'xc6vcx240t' is not a WebPack part.`
15			`WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue`
16			`to function, but you no longer qualify for Xilinx software updates or new releases.`
17
18			`----------------------------------------------------------------------`
19
20			`Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)`
21			`Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)`
22
23
24			`Device speed data version: "PRELIMINARY 1.04 2010-04-09".`
25
26
27
28			`Device Utilization Summary:`
29
30			`Slice Logic Utilization:`
31			`Number of Slice Registers: 10,769 out of 301,440 3%`
32			`Number used as Flip Flops: 10,769`
33			`Number used as Latches: 0`
34			`Number used as Latch-thrus: 0`
35			`Number used as AND/OR logics: 0`
36			`Number of Slice LUTs: 12,475 out of 150,720 8%`
37			`Number used as logic: 9,842 out of 150,720 6%`
38			`Number using O6 output only: 9,081`
39			`Number using O5 output only: 0`
40			`Number using O5 and O6: 761`
41			`Number used as ROM: 0`
42			`Number used as Memory: 0 out of 58,400 0%`
43			`Number used exclusively as route-thrus: 2,633`
44			`Number with same-slice register load: 2,633`
45			`Number with same-slice carry load: 0`
46			`Number with other load: 0`
47
48			`Slice Logic Distribution:`
49			`Number of occupied Slices: 3,214 out of 37,680 8%`
50			`Number of LUT Flip Flop pairs used: 12,527`
51			`Number with an unused Flip Flop: 5,031 out of 12,527 40%`
52			`Number with an unused LUT: 52 out of 12,527 1%`
53			`Number of fully used LUT-FF pairs: 7,444 out of 12,527 59%`
54			`Number of slice register sites lost`
55			`to control set restrictions: 0 out of 301,440 0%`
56
57			`A LUT Flip Flop pair for this architecture represents one LUT paired with`
58			`one Flip Flop within a slice. A control set is a unique combination of`
59			`clock, reset, set, and enable signals for a registered element.`
60			`The Slice Logic Distribution report is not meaningful if the design is`
61			`over-mapped for a non-slice resource or if Placement fails.`
62			`OVERMAPPING of BRAM resources should be ignored if the design is`
63			`over-mapped for a non-BRAM resource or if placement fails.`
64
65			`IO Utilization:`
66			`Number of bonded IOBs: 389 out of 400 97%`
67
68			`Specific Feature Utilization:`
69			`Number of RAMB36E1/FIFO36E1s: 0 out of 416 0%`
70			`Number of RAMB18E1/FIFO18E1s: 0 out of 832 0%`
71			`Number of BUFG/BUFGCTRLs: 2 out of 32 6%`
72			`Number used as BUFGs: 2`
73			`Number used as BUFGCTRLs: 0`
74			`Number of ILOGICE1/ISERDESE1s: 0 out of 720 0%`
75			`Number of OLOGICE1/OSERDESE1s: 0 out of 720 0%`
76			`Number of BSCANs: 0 out of 4 0%`
77			`Number of BUFHCEs: 0 out of 144 0%`
78			`Number of BUFIODQSs: 0 out of 72 0%`
79			`Number of BUFRs: 0 out of 36 0%`
80			`Number of CAPTUREs: 0 out of 1 0%`
81			`Number of DSP48E1s: 0 out of 768 0%`
82			`Number of EFUSE_USRs: 0 out of 1 0%`
83			`Number of GTXE1s: 0 out of 12 0%`
84			`Number of IBUFDS_GTXE1s: 0 out of 8 0%`
85			`Number of ICAPs: 0 out of 2 0%`
86			`Number of IDELAYCTRLs: 0 out of 18 0%`
87			`Number of IODELAYE1s: 0 out of 720 0%`
88			`Number of MMCM_ADVs: 0 out of 12 0%`
89			`Number of PCIE_2_0s: 0 out of 2 0%`
90			`Number of STARTUPs: 1 out of 1 100%`
91			`Number of SYSMONs: 0 out of 1 0%`
92			`Number of TEMAC_SINGLEs: 0 out of 1 0%`
93
94
95			`Overall effort level (-ol): High`
96			`Router effort level (-rl): High`
97
98			`Starting initial Timing Analysis. REAL time: 35 secs`
99			`Finished initial Timing Analysis. REAL time: 36 secs`
100
101			`Starting Router`
102
103
104			`Phase 1 : 77964 unrouted; REAL time: 42 secs`
105
106			`Phase 2 : 70512 unrouted; REAL time: 54 secs`
107
108			`Phase 3 : 26862 unrouted; REAL time: 1 mins 44 secs`
109
110			`Phase 4 : 26860 unrouted; (Setup:0, Hold:1, Component Switching Limit:0) REAL time: 1 mins 56 secs`
111
112			`Updating file: Top_PipelinedCipher.ncd with current fully routed design.`
113
114			`Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 30 secs`
115
116			`Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 30 secs`
117
118			`Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 30 secs`
119
120			`Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 30 secs`
121
122			`Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 30 secs`
123
124			`Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 38 secs`
125			`Total REAL time to Router completion: 2 mins 38 secs`
126			`Total CPU time to Router completion: 2 mins 42 secs`
127
128			`Partition Implementation Status`
129			`-------------------------------`
130
131			`No Partitions were found in this design.`
132
133			`-------------------------------`
134
135			`Generating "PAR" statistics.`
136
137			`**************************`
138			`Generating Clock Report`
139			`**************************`
140
141			`+---------------------+--------------+------+------+------------+-------------+`
142			`\| Clock Net \| Resource \|Locked\|Fanout\|Net Skew(ns)\|Max Delay(ns)\|`
143			`+---------------------+--------------+------+------+------------+-------------+`
144			`\| clk_BUFGP \| BUFGCTRL_X0Y0\| No \| 3213 \| 0.252 \| 1.834 \|`
145			`+---------------------+--------------+------+------+------------+-------------+`
146
147			`* Net Skew is the difference between the minimum and maximum routing`
148			`only delays for the net. Note this is different from Clock Skew which`
149			`is reported in TRCE timing report. Clock Skew is the difference between`
150			`the minimum and maximum path delays which includes logic delays.`
151
152			`Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)`
153
154			`Asterisk (*) preceding a constraint indicates it was not met.`
155			`This may be due to a setup or hold violation.`
156
157			`----------------------------------------------------------------------------------------------------------`
158			`Constraint \| Check \| Worst Case \| Best Case \| Timing \| Timing`
159			`\| \| Slack \| Achievable \| Errors \| Score`
160			`----------------------------------------------------------------------------------------------------------`
161			`TS_clk = PERIOD TIMEGRP "clk" 5 ns HIGH 5 \| SETUP \| 0.048ns\| 4.952ns\| 0\| 0`
162			`0% \| HOLD \| 0.006ns\| \| 0\| 0`
163			`----------------------------------------------------------------------------------------------------------`
164
165
166			`All constraints were met.`
167
168
169			`Generating Pad Report.`
170
171			`All signals are completely routed.`
172
173			`Total REAL time to PAR completion: 2 mins 46 secs`
174			`Total CPU time to PAR completion: 2 mins 49 secs`
175
176			`Peak Memory Usage: 1113 MB`
177
178			`Placer: Placement generated during map.`
179			`Routing: Completed - No errors found.`
180			`Timing: Completed - No errors found.`
181
182			`Number of error messages: 0`
183			`Number of warning messages: 0`
184			`Number of info messages: 0`
185
186			`Writing design to file Top_PipelinedCipher.ncd`
187
188
189
190			`PAR done!`

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[/] [aes-128_pipelined_encryption/] [trunk/] [reports/] [Top_PipelinedCipher.par] - Blame information for rev 2