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[/] [aes-encryption/] [trunk/] [aes_10cycle_10stage/] [test_bench_top.v] - Blame information for rev 2

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1 2 tariq786
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////     Test Bench for 10 cycle - 10 stage AES128-ENC           ////
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////                                                             ////
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////                                                             ////
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////  Author: Tariq Bashir Ahmad                                 ////
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////          tariq.bashir@gmail.com                             ////
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////                                                             ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010          Tariq Bashir Ahmad              ////   
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////                         http://www.ecs.umass.edu/~tbashir   ////
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////                                                             ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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`timescale 1 ns/1 ps
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module test;
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reg             clk;
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reg             rst;
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reg      aes_en;
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reg             kld;
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reg     [127:0]  key;
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reg     [127:0]  text_in;
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wire    [127:0]  text_out;
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wire            done;
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initial
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   begin
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        clk <=  0;
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        repeat(1) @(posedge clk);
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        rst <=  1;
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        aes_en <=  1;
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        repeat(5) @(posedge clk);
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        rst <=  0;
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        repeat(1) @(posedge clk);
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        kld             <= #1 1;
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//      repeat(1) @(posedge clk);
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        key             <=  128'h0;
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        text_in  <=  128'h00112233445566778899aabbccddeeff;
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        repeat(1) @(posedge clk);            //you need 2 cycles after loading the key and input
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        kld  <= #1 0;
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        repeat(2) @(posedge clk);
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        kld  <= #1 0;
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        key             <=  128'h00112233445566778899aabbccddeeff;
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        text_in  <=  128'h0;
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        repeat(1) @(posedge clk);
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        kld     <= #1 0;
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        repeat(20) @(posedge clk);
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        aes_en <=  0;
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        end
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aes_cipher_top uut(
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        .clk(           clk             ),
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        .rst(           rst             ),
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        .ld(            kld             ),
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        .done(          done            ),
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        .key(           key             ),
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        .text_in(       text_in         ),
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        .text_out(      text_out        ),
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        );
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initial
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        forever #15 clk = ~clk;
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initial
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        #2050 $stop;
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initial
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                $monitor($time," TEXT_OUT is %h, DONE is %b\n",text_out,done);
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endmodule
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