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[/] [aes-encryption/] [trunk/] [aes_5cycle_2stage/] [aes_cipher_top.v] - Blame information for rev 2

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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  AES Cipher Top Level                                       ////
4
////                                                             ////
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////                                                             ////
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////  Author: Rudolf Usselmann                                   ////
7
////          rudi@asics.ws                                      ////
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////                                                             ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org/cores/aes_core/  ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
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////                         www.asics.ws                        ////
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////                         rudi@asics.ws                       ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
19
//// restriction provided that this copyright statement is not   ////
20
//// removed from the file and that any derivative work contains ////
21
//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
27
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
38
 
39
//// Modified to achieve 5 cycles - stage  functionality             ////
40
//// By Tariq Bashir Ahmad                                                                       ////   
41
////  tariq.bashir@gmail.com                                                             ////
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////  http://www.ecs.umass.edu/~tbashir                                          ////
43
 
44
 
45
 
46
`timescale 1 ns/1 ps
47
 
48
module aes_cipher_top(clk, rst, ld, done, key, text_in, text_out,aes_en);
49
 
50
input           clk, rst;
51
input           ld;
52
output          done;
53
input   [127:0]  key;
54
input   [127:0]  text_in;
55
output  [127:0]  text_out;
56
 
57
input aes_en;
58
////////////////////////////////////////////////////////////////////
59
//
60
// Local Wires
61
//
62
 
63
wire    [31:0]   w0, w1, w2, w3, w4, w5, w6, w7;
64
/*wire  [127:0] key_odd,key_even;
65
*/
66
reg     [127:0]  text_in_r;
67
reg     [127:0]  text_out;
68
 
69
reg     [127:0]  text_out_temp;
70
 
71
reg     [7:0]    sa00, sa01, sa02, sa03;
72
reg     [7:0]    sa10, sa11, sa12, sa13;
73
reg     [7:0]    sa20, sa21, sa22, sa23;
74
reg     [7:0]    sa30, sa31, sa32, sa33;
75
 
76
wire    [7:0]    sa00_next, sa01_next, sa02_next, sa03_next;
77
wire    [7:0]    sa10_next, sa11_next, sa12_next, sa13_next;
78
wire    [7:0]    sa20_next, sa21_next, sa22_next, sa23_next;
79
wire    [7:0]    sa30_next, sa31_next, sa32_next, sa33_next;
80
 
81
wire    [7:0]    sa00_sub, sa01_sub, sa02_sub, sa03_sub;
82
wire    [7:0]    sa10_sub, sa11_sub, sa12_sub, sa13_sub;
83
wire  [7:0]      sa20_sub, sa21_sub, sa22_sub, sa23_sub;
84
wire    [7:0]    sa30_sub, sa31_sub, sa32_sub, sa33_sub;
85
 
86
wire    [7:0]    sa00_sr, sa01_sr, sa02_sr, sa03_sr;
87
wire    [7:0]    sa10_sr, sa11_sr, sa12_sr, sa13_sr;
88
wire    [7:0]    sa20_sr, sa21_sr, sa22_sr, sa23_sr;
89
wire    [7:0]    sa30_sr, sa31_sr, sa32_sr, sa33_sr;
90
 
91
wire    [7:0]    sa00_mc, sa01_mc, sa02_mc, sa03_mc;
92
wire    [7:0]    sa10_mc, sa11_mc, sa12_mc, sa13_mc;
93
wire    [7:0]    sa20_mc, sa21_mc, sa22_mc, sa23_mc;
94
wire    [7:0]    sa30_mc, sa31_mc, sa32_mc, sa33_mc;
95
 
96
 
97
wire    [7:0]    sa00_next_round2, sa01_next_round2, sa02_next_round2, sa03_next_round2;
98
wire    [7:0]    sa10_next_round2, sa11_next_round2, sa12_next_round2, sa13_next_round2;
99
wire    [7:0]    sa20_next_round2, sa21_next_round2, sa22_next_round2, sa23_next_round2;
100
wire    [7:0]    sa30_next_round2, sa31_next_round2, sa32_next_round2, sa33_next_round2;
101
 
102
wire    [7:0]    sa00_sub_round2, sa01_sub_round2, sa02_sub_round2, sa03_sub_round2;
103
wire    [7:0]    sa10_sub_round2, sa11_sub_round2, sa12_sub_round2, sa13_sub_round2;
104
wire  [7:0]      sa20_sub_round2, sa21_sub_round2, sa22_sub_round2, sa23_sub_round2;
105
wire    [7:0]    sa30_sub_round2, sa31_sub_round2, sa32_sub_round2, sa33_sub_round2;
106
 
107
wire    [7:0]    sa00_sr_round2, sa01_sr_round2, sa02_sr_round2, sa03_sr_round2;
108
wire    [7:0]    sa10_sr_round2, sa11_sr_round2, sa12_sr_round2, sa13_sr_round2;
109
wire    [7:0]    sa20_sr_round2, sa21_sr_round2, sa22_sr_round2, sa23_sr_round2;
110
wire    [7:0]    sa30_sr_round2, sa31_sr_round2, sa32_sr_round2, sa33_sr_round2;
111
 
112
wire    [7:0]    sa00_mc_round2, sa01_mc_round2, sa02_mc_round2, sa03_mc_round2;
113
wire    [7:0]    sa10_mc_round2, sa11_mc_round2, sa12_mc_round2, sa13_mc_round2;
114
wire    [7:0]    sa20_mc_round2, sa21_mc_round2, sa22_mc_round2, sa23_mc_round2;
115
wire    [7:0]    sa30_mc_round2, sa31_mc_round2, sa32_mc_round2, sa33_mc_round2;
116
 
117
 
118
 
119
 
120
reg             done, ld_r;
121
reg     [3:0]    dcnt;
122
reg             done2;
123
 
124
////////////////////////////////////////////////////////////////////
125
//
126
// Misc Logic
127
//
128
 
129
always @(posedge clk)
130
if(aes_en)
131
begin
132
        if(rst) begin dcnt <=  4'h0;     end
133
        else
134
        if(ld)  begin   dcnt <=  4'h6;   end
135
        else
136
        if(|dcnt) begin dcnt <=  dcnt - 4'h1;  end
137
 
138
end
139
 
140
always @(posedge clk) done <=  !(|dcnt[3:1]) & dcnt[0] & !ld;
141
always @(posedge clk) if(ld) text_in_r <=  text_in;
142
always @(posedge clk) ld_r <=  ld;
143
 
144
 
145
 
146
////////////////////////////////////////////////////////////////////
147
// key expansion
148
 
149
 
150
aes_key_expand_128 u0(
151
        .clk(           clk     ),
152
        .kld(           ld_r    ),
153
        .key(           key     ),
154
        .w0(            w0      ),
155
        .w1(            w1      ),
156
        .w2(            w2      ),
157
        .w3(            w3      ),
158
        .w4_reg(                w4      ),
159
        .w5_reg(                w5      ),
160
        .w6_reg(                w6      ),
161
        .w7_reg(                w7      )
162
                                                        );
163
/*assign key_odd  = {w0,w1,w2,w3};
164
assign key_even = {w4,w5,w6,w7};
165
*/
166
 
167
/*assign {w0,w1,w2,w3} = 128'h0;
168
 
169
assign {w4,w5,w6,w7} = 128'h62636363626363636263636362636363;
170
*/
171
// Initial Permutation (AddRoundKey)
172
//
173
/*
174
always @(posedge clk)
175
begin
176
  w0 <= w0_net;
177
  w1 <= w1_net;
178
  w2 <= w2_net;
179
  w3 <= w3_net;
180
  w4 <= w4_net;
181
  w5 <= w5_net;
182
  w6 <= w6_net;
183
  w7 <= w7_net;
184
end
185
*/
186
always @(posedge clk)
187
begin
188
        sa33 <=  ld_r ? text_in_r[007:000] ^ w3[07:00] : sa33_mc_round2 ^ w3[07:00];
189
        sa23 <=  ld_r ? text_in_r[015:008] ^ w3[15:08] : sa23_mc_round2 ^ w3[15:08];
190
        sa13 <=  ld_r ? text_in_r[023:016] ^ w3[23:16] : sa13_mc_round2 ^ w3[23:16];
191
        sa03 <=  ld_r ? text_in_r[031:024] ^ w3[31:24] : sa03_mc_round2 ^ w3[31:24];
192
        sa32 <=  ld_r ? text_in_r[039:032] ^ w2[07:00] : sa32_mc_round2 ^ w2[07:00];
193
        sa22 <=  ld_r ? text_in_r[047:040] ^ w2[15:08] : sa22_mc_round2 ^ w2[15:08];
194
        sa12 <=  ld_r ? text_in_r[055:048] ^ w2[23:16] : sa12_mc_round2 ^ w2[23:16];
195
        sa02 <=  ld_r ? text_in_r[063:056] ^ w2[31:24] : sa02_mc_round2 ^ w2[31:24];
196
        sa31 <=  ld_r ? text_in_r[071:064] ^ w1[07:00] : sa31_mc_round2 ^ w1[07:00];
197
        sa21 <=  ld_r ? text_in_r[079:072] ^ w1[15:08] : sa21_mc_round2 ^ w1[15:08];
198
        sa11 <=  ld_r ? text_in_r[087:080] ^ w1[23:16] : sa11_mc_round2 ^ w1[23:16];
199
        sa01 <=  ld_r ? text_in_r[095:088] ^ w1[31:24] : sa01_mc_round2 ^ w1[31:24];
200
        sa30 <=  ld_r ? text_in_r[103:096] ^ w0[07:00] : sa30_mc_round2 ^ w0[07:00];
201
        sa20 <=  ld_r ? text_in_r[111:104] ^ w0[15:08] : sa20_mc_round2 ^ w0[15:08];
202
        sa10 <=  ld_r ? text_in_r[119:112] ^ w0[23:16] : sa10_mc_round2 ^ w0[23:16];
203
        sa00 <=  ld_r ? text_in_r[127:120] ^ w0[31:24] : sa00_mc_round2 ^ w0[31:24];
204
 
205
                /*$strobe($time,": roundkeyodd = %h\n",{w0,w1,w2,w3});
206
                $strobe($time,": state is %h\n",{sa00, sa01, sa02, sa03,
207
                                                                                                         sa10, sa11, sa12, sa13,
208
                                                                                                         sa20, sa21, sa22, sa23,
209
                                                                                                         sa30, sa31, sa32, sa33});*/
210
 
211
end
212
 
213
////////////////////////////////////////////////////////////////////
214
//
215
// Modules instantiation
216
//
217
 
218
//sbox lookup
219
aes_sbox us00(  .a(     sa00    ), .d(  sa00_sub        ));
220
aes_sbox us01(  .a(     sa01    ), .d(  sa01_sub        ));
221
aes_sbox us02(  .a(     sa02    ), .d(  sa02_sub        ));
222
aes_sbox us03(  .a(     sa03    ), .d(  sa03_sub        ));
223
aes_sbox us10(  .a(     sa10    ), .d(  sa10_sub        ));
224
aes_sbox us11(  .a(     sa11    ), .d(  sa11_sub        ));
225
aes_sbox us12(  .a(     sa12    ), .d(  sa12_sub        ));
226
aes_sbox us13(  .a(     sa13    ), .d(  sa13_sub        ));
227
aes_sbox us20(  .a(     sa20    ), .d(  sa20_sub        ));
228
aes_sbox us21(  .a(     sa21    ), .d(  sa21_sub        ));
229
aes_sbox us22(  .a(     sa22    ), .d(  sa22_sub        ));
230
aes_sbox us23(  .a(     sa23    ), .d(  sa23_sub        ));
231
aes_sbox us30(  .a(     sa30    ), .d(  sa30_sub        ));
232
aes_sbox us31(  .a(     sa31    ), .d(  sa31_sub        ));
233
aes_sbox us32(  .a(     sa32    ), .d(  sa32_sub        ));
234
aes_sbox us33(  .a(     sa33    ), .d(  sa33_sub        ));
235
 
236
////////////////////////////////////////////////////////////////////
237
//
238
// Round Permutations
239
//
240
 
241
assign sa00_sr = sa00_sub;              //
242
assign sa01_sr = sa01_sub;              //no shift
243
assign sa02_sr = sa02_sub;              //
244
assign sa03_sr = sa03_sub;              //
245
 
246
assign sa10_sr = sa11_sub;              //
247
assign sa11_sr = sa12_sub;              // left shift by 1
248
assign sa12_sr = sa13_sub;              //
249
assign sa13_sr = sa10_sub;              //
250
 
251
assign sa20_sr = sa22_sub;              //
252
assign sa21_sr = sa23_sub;              //      left shift by 2
253
assign sa22_sr = sa20_sub;              //
254
assign sa23_sr = sa21_sub;              //
255
 
256
assign sa30_sr = sa33_sub;              //
257
assign sa31_sr = sa30_sub;              // left shift by 3
258
assign sa32_sr = sa31_sub;              //
259
assign sa33_sr = sa32_sub;              //
260
 
261
// mix column operation
262
assign {sa00_mc, sa10_mc, sa20_mc, sa30_mc}  = mix_col(sa00_sr,sa10_sr,sa20_sr,sa30_sr);
263
assign {sa01_mc, sa11_mc, sa21_mc, sa31_mc}  = mix_col(sa01_sr,sa11_sr,sa21_sr,sa31_sr);
264
assign {sa02_mc, sa12_mc, sa22_mc, sa32_mc}  = mix_col(sa02_sr,sa12_sr,sa22_sr,sa32_sr);
265
assign {sa03_mc, sa13_mc, sa23_mc, sa33_mc}  = mix_col(sa03_sr,sa13_sr,sa23_sr,sa33_sr);
266
 
267
//// add round key
268
assign sa00_next_round2 = sa00_mc ^ w4[31:24];
269
assign sa01_next_round2 = sa01_mc ^ w5[31:24];
270
assign sa02_next_round2 = sa02_mc ^ w6[31:24];
271
assign sa03_next_round2 = sa03_mc ^ w7[31:24];
272
assign sa10_next_round2 = sa10_mc ^ w4[23:16];
273
assign sa11_next_round2 = sa11_mc ^ w5[23:16];
274
assign sa12_next_round2 = sa12_mc ^ w6[23:16];
275
assign sa13_next_round2 = sa13_mc ^ w7[23:16];
276
assign sa20_next_round2 = sa20_mc ^ w4[15:08];
277
assign sa21_next_round2 = sa21_mc ^ w5[15:08];
278
assign sa22_next_round2 = sa22_mc ^ w6[15:08];
279
assign sa23_next_round2 = sa23_mc ^ w7[15:08];
280
assign sa30_next_round2 = sa30_mc ^ w4[07:00];
281
assign sa31_next_round2 = sa31_mc ^ w5[07:00];
282
assign sa32_next_round2 = sa32_mc ^ w6[07:00];
283
assign sa33_next_round2 = sa33_mc ^ w7[07:00];
284
 
285
 
286
always @(posedge clk)
287
 if(aes_en && ~rst)
288
begin
289
 
290
         /* $strobe($time,": roundkeyodd = %h, text_out_odd is %h\n",{w0,w1,w2,w3},text_out_temp);
291
          $strobe($time,": roundkeyeven is %h\n",{w4,w5,w6,w7});        */
292
          text_out_temp[127:120] <=  sa00_sr ^ w4[31:24];
293
          text_out_temp[095:088] <=  sa01_sr ^ w5[31:24];
294
     text_out_temp[063:056] <=  sa02_sr ^ w6[31:24];
295
          text_out_temp[031:024] <=  sa03_sr ^ w7[31:24];
296
          text_out_temp[119:112] <=  sa10_sr ^ w4[23:16];
297
          text_out_temp[087:080] <=  sa11_sr ^ w5[23:16];
298
          text_out_temp[055:048] <=  sa12_sr ^ w6[23:16];
299
          text_out_temp[023:016] <=  sa13_sr ^ w7[23:16];
300
          text_out_temp[111:104] <=  sa20_sr ^ w4[15:08];
301
          text_out_temp[079:072] <=  sa21_sr ^ w5[15:08];
302
          text_out_temp[047:040] <=  sa22_sr ^ w6[15:08];
303
          text_out_temp[015:008] <=  sa23_sr ^ w7[15:08];
304
          text_out_temp[103:096] <=  sa30_sr ^ w4[07:00];
305
          text_out_temp[071:064] <=  sa31_sr ^ w5[07:00];
306
          text_out_temp[039:032] <=  sa32_sr ^ w6[07:00];
307
          text_out_temp[007:000] <=  sa33_sr ^ w7[07:00];
308
end
309
 
310
 
311
 
312
 
313
//////////////////////  round i + 1 //////////////////////////////////
314
//sbox lookup
315
aes_sbox us00_round2(   .a(     sa00_next_round2        ), .d(  sa00_sub_round2 ));
316
aes_sbox us01_round2(   .a(     sa01_next_round2        ), .d(  sa01_sub_round2 ));
317
aes_sbox us02_round2(   .a(     sa02_next_round2        ), .d(  sa02_sub_round2 ));
318
aes_sbox us03_round2(   .a(     sa03_next_round2        ), .d(  sa03_sub_round2 ));
319
aes_sbox us10_round2(   .a(     sa10_next_round2        ), .d(  sa10_sub_round2 ));
320
aes_sbox us11_round2(   .a(     sa11_next_round2        ), .d(  sa11_sub_round2 ));
321
aes_sbox us12_round2(   .a(     sa12_next_round2        ), .d(  sa12_sub_round2 ));
322
aes_sbox us13_round2(   .a(     sa13_next_round2        ), .d(  sa13_sub_round2 ));
323
aes_sbox us20_round2(   .a(     sa20_next_round2        ), .d(  sa20_sub_round2 ));
324
aes_sbox us21_round2(   .a(     sa21_next_round2        ), .d(  sa21_sub_round2 ));
325
aes_sbox us22_round2(   .a(     sa22_next_round2        ), .d(  sa22_sub_round2 ));
326
aes_sbox us23_round2(   .a(     sa23_next_round2        ), .d(  sa23_sub_round2 ));
327
aes_sbox us30_round2(   .a(     sa30_next_round2        ), .d(  sa30_sub_round2 ));
328
aes_sbox us31_round2(   .a(     sa31_next_round2        ), .d(  sa31_sub_round2 ));
329
aes_sbox us32_round2(   .a(     sa32_next_round2        ), .d(  sa32_sub_round2 ));
330
aes_sbox us33_round2(   .a(     sa33_next_round2        ), .d(  sa33_sub_round2 ));
331
 
332
 
333
// Round Permutations
334
//
335
 
336
assign sa00_sr_round2 = sa00_sub_round2;                //
337
assign sa01_sr_round2 = sa01_sub_round2;                //no shift
338
assign sa02_sr_round2 = sa02_sub_round2;                //
339
assign sa03_sr_round2 = sa03_sub_round2;                //
340
 
341
assign sa10_sr_round2 = sa11_sub_round2;                //
342
assign sa11_sr_round2 = sa12_sub_round2;                // left shift by 1
343
assign sa12_sr_round2 = sa13_sub_round2;                //
344
assign sa13_sr_round2 = sa10_sub_round2;                //
345
 
346
assign sa20_sr_round2 = sa22_sub_round2;                //
347
assign sa21_sr_round2 = sa23_sub_round2;                //      left shift by 2
348
assign sa22_sr_round2 = sa20_sub_round2;                //
349
assign sa23_sr_round2 = sa21_sub_round2;                //
350
 
351
assign sa30_sr_round2 = sa33_sub_round2;                //
352
assign sa31_sr_round2 = sa30_sub_round2;                // left shift by 3
353
assign sa32_sr_round2 = sa31_sub_round2;                //
354
assign sa33_sr_round2 = sa32_sub_round2;                //
355
 
356
// mix column operation
357
assign {sa00_mc_round2, sa10_mc_round2, sa20_mc_round2, sa30_mc_round2}  = mix_col(sa00_sr_round2,sa10_sr_round2,sa20_sr_round2,sa30_sr_round2);
358
assign {sa01_mc_round2, sa11_mc_round2, sa21_mc_round2, sa31_mc_round2}  = mix_col(sa01_sr_round2,sa11_sr_round2,sa21_sr_round2,sa31_sr_round2);
359
assign {sa02_mc_round2, sa12_mc_round2, sa22_mc_round2, sa32_mc_round2}  = mix_col(sa02_sr_round2,sa12_sr_round2,sa22_sr_round2,sa32_sr_round2);
360
assign {sa03_mc_round2, sa13_mc_round2, sa23_mc_round2, sa33_mc_round2}  = mix_col(sa03_sr_round2,sa13_sr_round2,sa23_sr_round2,sa33_sr_round2);
361
 
362
////////////////////////////////////////////////////////////////////
363
//
364
// Final text output
365
//
366
 
367
 
368
always @(posedge clk)
369
 if(aes_en && ~rst)
370
 begin
371
                /*  $strobe($time,": round_key2 is %h\n",{w4,w5,w6,w7});
372
                  $strobe($time,": roundkeyeven = %h, text_out_even is %h\n",{w4,w5,w6,w7},text_out);*/
373
                  text_out[127:120] <=  sa00_sr_round2 ^ w0[31:24];
374
                  text_out[095:088] <=  sa01_sr_round2 ^ w1[31:24];
375
                  text_out[063:056] <=  sa02_sr_round2 ^ w2[31:24];
376
                  text_out[031:024] <=  sa03_sr_round2 ^ w3[31:24];
377
                  text_out[119:112] <=  sa10_sr_round2 ^ w0[23:16];
378
                  text_out[087:080] <=  sa11_sr_round2 ^ w1[23:16];
379
                  text_out[055:048] <=  sa12_sr_round2 ^ w2[23:16];
380
                  text_out[023:016] <=  sa13_sr_round2 ^ w3[23:16];
381
                  text_out[111:104] <=  sa20_sr_round2 ^ w0[15:08];
382
                  text_out[079:072] <=  sa21_sr_round2 ^ w1[15:08];
383
                  text_out[047:040] <=  sa22_sr_round2 ^ w2[15:08];
384
                  text_out[015:008] <=  sa23_sr_round2 ^ w3[15:08];
385
                  text_out[103:096] <=  sa30_sr_round2 ^ w0[07:00];
386
                  text_out[071:064] <=  sa31_sr_round2 ^ w1[07:00];
387
                  text_out[039:032] <=  sa32_sr_round2 ^ w2[07:00];
388
                  text_out[007:000] <=  sa33_sr_round2 ^ w3[07:00];
389
        end
390
 
391
 
392
always @(posedge clk)
393
        begin
394
/*      $strobe($time,": text_out_temp is %h\n",text_out_temp);
395
 
396
 
397
*/      /*
398
        $strobe($time,": subbytes is %h\n",{sa00_sub, sa01_sub, sa02_sub, sa03_sub,
399
                                                                                                         sa10_sub, sa11_sub, sa12_sub, sa13_sub,
400
                                                                                                         sa20_sub, sa21_sub, sa22_sub, sa23_sub,
401
                                                                                                         sa30_sub, sa31_sub, sa32_sub, sa33_sub});
402
 
403
        $strobe($time,": shiftrows is %h\n",{sa00_sr, sa01_sr, sa02_sr, sa03_sr,
404
                                                                                                          sa10_sr, sa11_sr, sa12_sr, sa13_sr,
405
                                                                                                          sa20_sr, sa21_sr, sa22_sr, sa23_sr,
406
                                                                                                          sa30_sr, sa31_sr, sa32_sr, sa33_sr});
407
 
408
        $strobe($time,": mixcolumn is %h\n",{sa00_mc, sa01_mc, sa02_mc, sa03_mc,
409
                                                                                                          sa10_mc, sa11_mc, sa12_mc, sa13_mc,
410
                                                                                                          sa20_mc, sa21_mc, sa22_mc, sa23_mc,
411
                                                                                                          sa30_mc, sa31_mc, sa32_mc, sa33_mc});
412
 
413
        $strobe($time,": sa_next_into_even is %h\n",{sa00_next_round2, sa01_next_round2, sa02_next_round2, sa03_next_round2,
414
                                                                                                                                 sa10_next_round2, sa11_next_round2, sa12_next_round2, sa13_next_round2,
415
                                                                                                                                 sa20_next_round2, sa21_next_round2, sa22_next_round2, sa23_next_round2,
416
                                                                                                                                 sa30_next_round2, sa31_next_round2, sa32_next_round2, sa33_next_round2});
417
 
418
        $strobe($time,": subbytes_e is %h\n",{sa00_sub_round2, sa01_sub_round2, sa02_sub_round2, sa03_sub_round2,
419
                                                                                                         sa10_sub_round2, sa11_sub_round2, sa12_sub_round2, sa13_sub_round2,
420
                                                                                                         sa20_sub_round2, sa21_sub_round2, sa22_sub_round2, sa23_sub_round2,
421
                                                                                                         sa30_sub_round2, sa31_sub_round2, sa32_sub_round2, sa33_sub_round2});
422
 
423
        $strobe($time,": shiftrows_e is %h\n",{sa00_sr_round2, sa01_sr_round2, sa02_sr_round2, sa03_sr_round2,
424
                                                                                                          sa10_sr_round2, sa11_sr_round2, sa12_sr_round2, sa13_sr_round2,
425
                                                                                                          sa20_sr_round2, sa21_sr_round2, sa22_sr_round2, sa23_sr_round2,
426
                                                                                                          sa30_sr_round2, sa31_sr_round2, sa32_sr_round2, sa33_sr_round2});
427
 
428
        $strobe($time,": mixcolumn_e is %h\n",{sa00_mc_round2, sa01_mc_round2, sa02_mc_round2, sa03_mc_round2,
429
                                                                                                          sa10_mc_round2, sa11_mc_round2, sa12_mc_round2, sa13_mc_round2,
430
                                                                                                          sa20_mc_round2, sa21_mc_round2, sa22_mc_round2, sa23_mc_round2,
431
                                                                                                          sa30_mc_round2, sa31_mc_round2, sa32_mc_round2, sa33_mc_round2});
432
        */
433
        end
434
 
435
 
436
/*
437
always @(posedge clk)
438
       begin
439
                                if(done)
440
                                                begin
441
                                                        text_out_64 <= text_out[127:64];
442
//                                                      done2 <= 1;
443
                                                end
444
                                else if(~done)
445
                                                        text_out_64 <= text_out[63:0];
446
                end
447
        */
448
 
449
/*
450
always @(posedge clk)
451
                         begin
452
                                if(done2)
453
                                        begin
454
                                                text_out_64 <= text_out[63:0];
455
                                        end
456
                 end
457
*/
458
////////////////////////////////////////////////////////////////////
459
//
460
// Generic Functions
461
//
462
 
463
function [31:0] mix_col;
464
input   [7:0]    s0,s1,s2,s3;
465
//reg   [7:0]   s0_o,s1_o,s2_o,s3_o;
466
begin
467
mix_col[31:24]=xtime(s0)^xtime(s1)^s1^s2^s3;
468
mix_col[23:16]=s0^xtime(s1)^xtime(s2)^s2^s3;
469
mix_col[15:08]=s0^s1^xtime(s2)^xtime(s3)^s3;
470
mix_col[07:00]=xtime(s0)^s0^s1^s2^xtime(s3);
471
end
472
endfunction
473
 
474
function [7:0] xtime;
475
input [7:0] b; xtime={b[6:0],1'b0}^(8'h1b&{8{b[7]}});
476
endfunction
477
 
478
 
479
 
480
endmodule
481
 
482
 
483
 

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