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[/] [aes-encryption/] [trunk/] [aes_5cycle_2stage/] [aes_rcon.v] - Blame information for rev 2

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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  AES RCON Block                                             ////
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////                                                             ////
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////                                                             ////
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////  Author: Rudolf Usselmann                                   ////
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////          rudi@asics.ws                                      ////
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////                                                             ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org/cores/aes_core/  ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
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////                         www.asics.ws                        ////
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////                         rudi@asics.ws                       ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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`timescale 1 ns/1 ps
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module aes_rcon(clk, kld,out,out2);
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input           clk;
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input           kld;
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output reg  [7:0] out,out2;
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reg     [3:0]    rcnt_reg;
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wire    [3:0]    rcnt_next;
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assign rcnt_next = (kld) ? 0 : rcnt_reg+2;
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always @*
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begin
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                out  = kld ? 8'h01:frcon(rcnt_next-1);
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                out2 = kld ? 8'h01:frcon(rcnt_next);
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end
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always @(posedge clk)
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begin
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                rcnt_reg <= rcnt_next;
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/*              $strobe($time,": out is %h, out2 is %h\n",out,out2);
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*/
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end
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function [7:0]   frcon;
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input   [3:0]    i;
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case(i) // synopsys parallel_case
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   4'h0: frcon=8'h01;           //1
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   4'h1: frcon=8'h02;           //x
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   4'h2: frcon=8'h04;           //x^2
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   4'h3: frcon=8'h08;           //x^3
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   4'h4: frcon=8'h10;           //x^4
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   4'h5: frcon=8'h20;           //x^5
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   4'h6: frcon=8'h40;           //x^6
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   4'h7: frcon=8'h80;           //x^7
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   4'h8: frcon=8'h1b;           //x^8
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   4'h9: frcon=8'h36;           //x^9
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   default: frcon=8'h00;
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endcase
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endfunction
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endmodule

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