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csantifort |
# ----------------------------------------------------------------
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# //
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# FPGA synthesis Makefile //
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# //
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# This file is part of the Amber project //
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# http://www.opencores.org/project,amber //
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# //
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# Description //
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# Runs a full FPGA synthesis of the Amber system. //
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# //
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# Author(s): //
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# - Conor Santifort, csantifort.amber@gmail.com //
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# //
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#/ ///////////////////////////////////////////////////////////////
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# //
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# Copyright (C) 2010 Authors and OPENCORES.ORG //
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# //
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# This source file may be used and distributed without //
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# restriction provided that this copyright statement is not //
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# removed from the file and that any derivative work contains //
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# the original copyright notice and the associated disclaimer. //
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# //
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# This source file is free software; you can redistribute it //
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# and/or modify it under the terms of the GNU Lesser General //
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# Public License as published by the Free Software Foundation; //
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# either version 2.1 of the License, or (at your option) any //
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# later version. //
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# //
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# This source is distributed in the hope that it will be //
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# useful, but WITHOUT ANY WARRANTY; without even the implied //
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# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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# PURPOSE. See the GNU Lesser General Public License for more //
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# details. //
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# //
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# You should have received a copy of the GNU Lesser General //
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# Public License along with this source; if not, download it //
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# from http://www.opencores.org/lgpl.shtml //
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# //
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# ----------------------------------------------------------------
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csantifort |
# ----------------------------------------------------
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csantifort |
# Environment Configuration
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# ----------------------------------------------------
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csantifort |
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# Directories
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BIN_FOLDER = ../bin
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LOG_FOLDER = ../logs
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BITFILE_FOLDER = ../bitfiles
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csantifort |
BOOT_LOADER_ETHMAC = 1
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csantifort |
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# Can supply different work directories
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# for multiple runs in parallel
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ifdef WORK
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WORK_FOLDER = ../$(WORK)
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else
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WORK_FOLDER = ../work0
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endif
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csantifort |
ifdef BOOT_LOADER_ETHMAC
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BOOT_LOADER_DIR = ../../../sw/boot-loader-ethmac
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BOOT_LOADER_DEF = BOOT_LOADER_ETHMAC
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else
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BOOT_LOADER_DIR = ../../../sw/boot-loader-serial
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BOOT_LOADER_DEF =
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endif
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VERILOG_INCLUDE_PATH = ../../vlog/lib ../../vlog/tb $(BOOT_LOADER_DIR)
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# Name of top level verilog file (must be the same as its module name)
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RTL_TOP = system
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# ----------------------------------------------------
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# Build Configuration
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# ----------------------------------------------------
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# AMBER_CLK_DIVIDER
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# Sets the system clock frequency
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# For Spartan-6 divide 800MHz by this number to get the frequency
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# e.g. AMBER_CLK_DIVIDER=24
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# 800 MHz / 24 = 33.33 MHz
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# For Virtex-6 divide 1200MHz by this number to get the frequency
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# Select either the A23 or A25 core
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ifdef A25
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AMBER_CORE = AMBER_A25_CORE
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else
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AMBER_CORE = AMBER_A23_CORE
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endif
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# The spartan6 device used on SP605 Development board
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XILINX_FPGA = xc6slx45tfgg484-3
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XST_DEFINES = XILINX_FPGA XILINX_SPARTAN6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=21 $(BOOT_LOADER_DEF)
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# Xilinx placement and timing constraints
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XST_CONST_FILE = xs6_constraints.ucf
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# List of verilog source files for Xilinx Spartan-6 device
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XST_PROJ_FILE = xs6_source_files.prj
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# ----------------------------------------------------
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# Focus on speed or area
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# ----------------------------------------------------
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#OPT = area
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OPT = speed
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# ----------------------------------------------------
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# Xilinx XST Compile Options
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# ----------------------------------------------------
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XST_OPTIONS = -vlgincdir {$(VERILOG_INCLUDE_PATH)} \
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-ifmt mixed \
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-ofmt NGC \
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-p $(XILINX_FPGA) \
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-opt_mode $(OPT) \
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-opt_level 2 \
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-power NO \
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-iuc NO \
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-keep_hierarchy NO \
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-rtlview Yes \
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-glob_opt AllClockNets \
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-read_cores YES \
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-write_timing_constraints NO \
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-cross_clock_analysis NO \
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-hierarchy_separator / \
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-bus_delimiter \<\> \
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-case maintain \
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-slice_utilization_ratio 100 \
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-bram_utilization_ratio 100 \
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-dsp_utilization_ratio 100 \
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-fsm_extract YES \
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-fsm_encoding Auto \
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-safe_implementation No \
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-fsm_style lut \
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-ram_extract Yes \
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-ram_style Auto \
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-rom_extract Yes \
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-shreg_extract YES \
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-rom_style Auto \
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-auto_bram_packing NO \
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-resource_sharing YES \
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-async_to_sync NO \
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-max_fanout 10000 \
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-bufg 32 \
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-register_duplication YES \
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-register_balancing No \
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-optimize_primitives NO \
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-use_clock_enable Auto \
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-use_sync_set Auto \
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-use_sync_reset Auto \
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-iob auto \
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-equivalent_register_removal YES \
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-slice_utilization_ratio_maxmargin 5
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# ----------------------------------------------------
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RUN_ID = $(shell cat $(WORK_FOLDER)/run_id.txt)
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MAP_SEED = $(shell $(BIN_FOLDER)/increment_seed.sh $(WORK_FOLDER)/seed.txt)
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# ----------------------------------------------------
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all : bitgen trce
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new : clean all
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map : cleanmap all
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help :
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@echo ""
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@echo "Valid targets:"
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@echo " new Start a new run with a new ID"
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@echo " all Continue last run from where ever it left off"
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@echo " map Rerun the map and par with a new seed"
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@echo " clean Delete all temporary files"
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@echo " bitgen Create a bitfile. Don't run trce"
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@echo " trce Running timing analysis. Don't run buitgen"
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@echo " help Print this message"
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@echo ""
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csantifort |
@echo "Optional switches: A25=1 WORK="
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@echo "e.g. > make A25=1 WORK=work1 map"
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csantifort |
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clean :
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rm -Rf $(WORK_FOLDER)/*
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cleanmap :
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if [ -f $(WORK_FOLDER)/$(RTL_TOP).map.ncd ]; then rm $(WORK_FOLDER)/$(RTL_TOP).map.ncd; fi
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bitgen : $(WORK_FOLDER)/$(RTL_TOP).bit
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trce : $(WORK_FOLDER)/$(RTL_TOP).trc.twr
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# ----------------------------------------------------
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# trce
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# ----------------------------------------------------
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# Can be done before or after bitgen
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$(WORK_FOLDER)/$(RTL_TOP).trc.twr : $(WORK_FOLDER)/$(RTL_TOP).ncd
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\
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cd $(WORK_FOLDER); \
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trce -v 5 -l 5 -n 5 -xml $(RTL_TOP) $(RTL_TOP).ncd \
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-o $(WORK_FOLDER)/$(RTL_TOP).trc.twr \
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$(RTL_TOP).pcf
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cp $(WORK_FOLDER)/$(RTL_TOP).trc.twr $(LOG_FOLDER)/$(RTL_TOP).trc.$(RUN_ID).twr
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# ----------------------------------------------------
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# bitgen
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# ----------------------------------------------------
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$(WORK_FOLDER)/$(RTL_TOP).bit : $(WORK_FOLDER)/$(RTL_TOP).ncd
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\
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cd $(WORK_FOLDER); \
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bitgen -intstyle xflow -f $(BIN_FOLDER)/bitfile_config.ut $(RTL_TOP).ncd
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cp $(WORK_FOLDER)/$(RTL_TOP).bit $(BITFILE_FOLDER)/$(RTL_TOP).$(RUN_ID).bit
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mv $(WORK_FOLDER)/$(RTL_TOP).bgn $(LOG_FOLDER)/$(RTL_TOP).bit.$(RUN_ID).bgn
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# ----------------------------------------------------
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# par
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# ----------------------------------------------------
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# -xe c = Extra Effort, continue on Impossible
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# -p means don't run the placer. We use map as the placer
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# -k = Re-entrant route. Keep the current placement. Continue the routing
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# using the existing routing as a starting point.
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$(WORK_FOLDER)/$(RTL_TOP).ncd : $(WORK_FOLDER)/$(RTL_TOP).map.ncd
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\
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cd $(WORK_FOLDER); \
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par -intstyle xflow -w -k -ol high $(RTL_TOP).map.ncd $(RTL_TOP).ncd $(RTL_TOP).pcf
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cp $(WORK_FOLDER)/$(RTL_TOP)_pad.txt $(LOG_FOLDER)/$(RTL_TOP).pad.$(RUN_ID).txt
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# ----------------------------------------------------
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# map
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# ----------------------------------------------------
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$(WORK_FOLDER)/$(RTL_TOP).map.ncd : $(WORK_FOLDER)/$(RTL_TOP).ngd
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cd $(WORK_FOLDER); \
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csantifort |
map -intstyle xflow \
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-p $(XILINX_FPGA) \
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-ol high \
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-t $(MAP_SEED) \
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-w \
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-ignore_keep_hierarchy \
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csantifort |
-timing \
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-detail \
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-register_duplication on \
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-lc auto \
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-xe c -mt off -ir off \
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-pr off -power off \
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-o $(RTL_TOP).map.ncd \
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$(RTL_TOP).ngd \
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csantifort |
$(RTL_TOP).pcf
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cp $(WORK_FOLDER)/$(RTL_TOP).map.mrp $(LOG_FOLDER)/$(RTL_TOP).map.$(RUN_ID).mrp
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csantifort |
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# ----------------------------------------------------
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# ngdbuild
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# ----------------------------------------------------
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$(WORK_FOLDER)/$(RTL_TOP).ngd : $(WORK_FOLDER)/$(RTL_TOP).ngc $(BIN_FOLDER)/$(XST_CONST_FILE)
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cd $(WORK_FOLDER); \
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ngdbuild -intstyle xflow -verbose -p $(XILINX_FPGA) \
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-dd _ngo -nt on \
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csantifort |
-uc $(BIN_FOLDER)/$(XST_CONST_FILE) $(RTL_TOP).ngc $(RTL_TOP).ngd
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csantifort |
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# ----------------------------------------------------
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# xst
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# ----------------------------------------------------
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# Note -iobuf YES is needed for the top-level verilog
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# module synthesis
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csantifort |
$(WORK_FOLDER)/$(RTL_TOP).ngc : $(WORK_FOLDER)/run_id.txt $(XST_PROJ_FILE)
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@echo "work: $(WORK_FOLDER)" > $(LOG_FOLDER)/$(RTL_TOP).cfg.$(RUN_ID).txt
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@echo "$(XST_DEFINES)" >> $(LOG_FOLDER)/$(RTL_TOP).cfg.$(RUN_ID).txt
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csantifort |
export XST_DESIGN=$(RTL_TOP)
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export XST_OFN=$(RTL_TOP)
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rm -Rf $(WORK_FOLDER)/$(RTL_TOP)xst $(WORK_FOLDER)/_ngo
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mkdir -p $(WORK_FOLDER)/$(RTL_TOP)xst/tmp $(WORK_FOLDER)/_ngo
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echo "work" > $(WORK_FOLDER)/$(RTL_TOP).lso
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echo "set -tmpdir ./$(RTL_TOP)xst/tmp" > $(WORK_FOLDER)/$(RTL_TOP).xst
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echo "set -xsthdpdir ./$(RTL_TOP)xst" >> $(WORK_FOLDER)/$(RTL_TOP).xst
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echo "run -ifn $(BIN_FOLDER)/$(XST_PROJ_FILE)" >> $(WORK_FOLDER)/$(RTL_TOP).xst
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echo "-ofn $(RTL_TOP) -top $(RTL_TOP)" >> $(WORK_FOLDER)/$(RTL_TOP).xst
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echo "-lso ./$(RTL_TOP).lso" >> $(WORK_FOLDER)/$(RTL_TOP).xst
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echo $(XST_OPTIONS) >> $(WORK_FOLDER)/$(RTL_TOP).xst
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echo "-iobuf YES" >> $(WORK_FOLDER)/$(RTL_TOP).xst
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csantifort |
echo "-define { $(XST_DEFINES) }" >> $(WORK_FOLDER)/$(RTL_TOP).xst
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csantifort |
cd $(WORK_FOLDER); \
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xst -intstyle xflow -ifn ./$(RTL_TOP).xst -ofn $(LOG_FOLDER)/$(RTL_TOP).xst.$(RUN_ID).srp
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# ----------------------------------------------------
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# Generate the Run ID, initial Map seed
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# Recompile the boot-loader program - it gets build
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# into the FPGA's RamBlocks and uses the run_id as
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# the version number
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# ----------------------------------------------------
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$(WORK_FOLDER)/run_id.txt :
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test -e $(WORK_FOLDER) || mkdir $(WORK_FOLDER)
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test -e $(LOG_FOLDER) || mkdir $(LOG_FOLDER)
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test -e $(BITFILE_FOLDER) || mkdir $(BITFILE_FOLDER)
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echo 0 > $(WORK_FOLDER)/seed.txt
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date +%Y%m%d%H%M%S > $(WORK_FOLDER)/run_id.txt
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$(BIN_FOLDER)/set_fpga_version.sh $(WORK_FOLDER)/run_id.txt
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csantifort |
$(MAKE) -C $(BOOT_LOADER_DIR) clean
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$(MAKE) -C $(BOOT_LOADER_DIR)
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csantifort |
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