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[/] [amber/] [trunk/] [hw/] [tests/] [change_sbits.S] - Blame information for rev 2

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1 2 csantifort
/*****************************************************************
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//                                                              //
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//  Amber 2 Core Instruction Test                               //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Tests movs where the destination register is r15, the pc    //
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//  Depending on the processor mode and whether the s bit is    //
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//  set or not, some or none of the status bits will change.    //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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*****************************************************************/
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#include "amber_registers.h"
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        .section .text
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        .globl  main
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main:
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        @ ------------------------------------------------------------------------
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        @ In supervisor mode, change to user mode
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        ldr     r0, UserMode
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        @ set the condition flags
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        orr     r0, r0, #0xf0000000
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        @ set one of the interrupt masks
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        orr     r0, r0, #0x04000000
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        ldr     r1, =1f
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        ldr     r2, PCMask
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        and     r2, r1, r2
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        orr     r3, r2, r0
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        movs    pc, r3
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        @ Check that the jump works correctly
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        b       testfail
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        b       testfail
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1:      b       2f
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        b       testfail
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        b       testfail
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        @ Now check that the status bits are changed correctly
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2:      mov     r8, pc
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        ldr     r9, PCMask
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        bic     r9, r8, r9
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        ldr     r12, ExpectedBits1
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        cmp     r9, r12
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        movne   r10, #20
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        bne     testfail
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        @ ------------------------------------------------------------------------
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        @ Test that in user mode, only the condition status bit
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        @ and the pc can be changed
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        @ In User mode, change to Supervisor mode (this isn't allowed and will fail)
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        ldr     r0, SupervisorMode
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        @ set the condition flags
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        orr     r0, r0, #0x30000000
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        @ set one of the interrupt masks
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        orr     r0, r0, #0x08000000
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        ldr     r1, =3f
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        ldr     r2, PCMask
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        and     r2, r1, r2
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        orr     r3, r2, r0
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        movs    pc, r3
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        @ Check that the jump works correctly
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        b       testfail
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        b       testfail
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3:      b       4f
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        b       testfail
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        b       testfail
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        @ Now check that the status bits are changed correctly
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4:      mov     r8, pc
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        ldr     r9, PCMask
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        bic     r9, r8, r9
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        ldr     r12, ExpectedBits2
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        cmp     r9, r12
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        movne   r10, #30
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        bne     testfail
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        @ ------------------------------------------------------------------------
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        @ Test that in user mode, only the pc changes when the s bit is not set
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        mov     r12, pc     @ remeber the current pc status bits
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        ldr     r9, PCMask
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        bic     r12, r12, r9
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        ldr     r0, UserMode
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        @ set the condition flags
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        orr     r0, r0, #0xc0000000
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        ldr     r1, =5f
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        ldr     r2, PCMask
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        and     r2, r1, r2
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        orr     r3, r2, r0
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        mov     pc, r3
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        @ Check that the jump works correctly
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        b       testfail
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        b       testfail
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5:      b       6f
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        b       testfail
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        b       testfail
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        @ Now check that the status bits are not changed
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6:      mov     r8, pc
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        ldr     r9, PCMask
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        bic     r9, r8, r9
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        cmp     r9, r12
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        movne   r10, #40
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        bne     testfail
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        b       testpass
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testfail:
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        ldr     r11, AdrTestStatus
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        str     r10, [r11]
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        b       testfail
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testpass:
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        ldr     r11, AdrTestStatus
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        mov     r10, #17
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        str     r10, [r11]
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        b       testpass
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/* Write 17 to this address to generate a Test Passed message */
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AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
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/* Switch to user mode */
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UserMode:       .word  0x00000000
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SupervisorMode: .word  0x00000003
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PCMask:         .word  0x03fffffc
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ExpectedBits1:  .word  0xf4000000
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ExpectedBits2:  .word  0x34000000
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ExpectedBits3:  .word  0x34000000
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/* ========================================================================= */
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/* ========================================================================= */
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